參數(shù)資料
型號(hào): P89LPC904FD
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: 8-bit microcontrollers with two-clock accelerated 80C51 core 1 kB 3 V byte-erasable Flash with 8-bit A/D converter
中文描述: 8-BIT, FLASH, 12 MHz, MICROCONTROLLER, PDSO8
封裝: 3.90 MM, PLASTIC, MS-012, SOT-96-1, SO-8
文件頁(yè)數(shù): 24/41頁(yè)
文件大?。?/td> 190K
代理商: P89LPC904FD
Philips Semiconductors
P89LPC904
8-bit microcontrollers with two-clock accelerated 80C51 core
Preliminary data
Rev. 02 — 25 June 2004
24 of 41
9397 750 13521
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
8.15.1
Idle mode
Idle mode leaves peripherals running in order to allow them to activate the processor
when an interrupt is generated. Any enabled interrupt source or reset may terminate
Idle mode.
8.15.2
Power-down mode
The Power-down mode stops the oscillator in order to minimize power consumption.
The P89LPC904 exits Power-down mode via any reset, or certain interrupts. In
Power-down mode, the power supply voltage may be reduced to the RAM keep-alive
voltage V
RAM
. This retains the RAM contents at the point where Power-down mode
was entered. SFR contents are not guaranteed after V
DD
has been lowered to V
RAM
,
therefore it is highly recommended to wake up the processor via reset in this case.
V
DD
must be raised to within the operating range before the Power-down mode is
exited.
Some chip functions continue to operate and draw power during Power-down mode,
increasing the total power used during Power-down. These include: Brownout detect,
Watchdog Timer, Comparators (note that Comparators can be powered-down
separately), and Real-Time Clock (RTC)/System Timer. The internal RC oscillator is
disabled unless both the RC oscillator has been selected as the system clock
and
the
RTC is enabled.
8.15.3
Total Power-down mode
This is the same as Power-down mode except that the brownout detection circuitry
and the voltage comparators are also disabled to conserve additional power. The
internal RC oscillator is disabled unless both the RC oscillator has been selected as
the system clock
and
the RTC is enabled. If the internal RC oscillator is used to clock
the RTC during Power-down, there will be high power consumption. Please use an
external low frequency clock to achieve low power with the Real-Time Clock running
during Power-down.
8.16 Reset
The P1.5/RST pin can function as either an active-LOW reset input or as a digital
input, P1.5. The RPE (Reset Pin Enable) bit in UCFG1, when set to logic 1, enables
the external reset input function on P1.5. When cleared, P1.5 may be used as an
input pin.
Remark:
During a power-up sequence, the RPE selection is overridden and this pin
will always function as a reset input.
An external circuit connected to this pin
should not hold this pin LOW during a power-on sequence as this will keep the
device in reset.
After power-up this input will function either as an external reset
input or as a digital input as defined by the RPE bit. Only a power-up reset will
temporarily override the selection defined by RPE bit. Other sources of reset will not
override the RPE bit.
Remark:
During a power cycle, V
DD
must fall below V
POR
(see
Table 8 “DC electrical
characteristics”
) before power is reapplied, in order to ensure a power-on reset.
相關(guān)PDF資料
PDF描述
P89LPC9102 8-bit microcontrollers with two-clock accelerated 80C51 core 1 kB 3 V byte-erasable Flash with 8-bit A/D converter
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