參數(shù)資料
型號(hào)： P89LPC904FD
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 8-bit microcontrollers with two-clock accelerated 80C51 core 1 kB 3 V byte-erasable Flash with 8-bit A/D converter
中文描述： 8-BIT, FLASH, 12 MHz, MICROCONTROLLER, PDSO8
封裝： 3.90 MM, PLASTIC, MS-012, SOT-96-1, SO-8
文件頁(yè)數(shù)： 13/41頁(yè)
文件大?。?/td> 190K
代理商： P89LPC904FD
Philips Semiconductors
P89LPC904
8-bit microcontrollers with two-clock accelerated 80C51 core
Preliminary data
Rev. 02 — 25 June 2004
13 of 41
9397 750 13521
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
8.
Functional description
Remark:
Please refer to the P89LPC904 User’s Manualfor a more detailed
functional description.
8.1 Enhanced CPU
The P89LPC904 uses an enhanced 80C51 CPU which runs at 6 times the speed of
standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and
most instructions execute in one or two machine cycles.
8.2 Clocks
8.2.1
Clock definitions
The P89LPC904 device has internal clocks as defined below:
OSCCLK —
Input to the DIVM clock divider. OSCCLK is selected from one of the
clock sources (see
Figure 4
) and can also be optionally divided to a slower frequency
(see
Section 8.7 “CPU CLOCK (CCLK) modification: DIVM register”
).
Note:
f
ext
is defined as the OSCCLK frequency.
CCLK —
CPU clock; output of the clock divider. There are two CCLK cycles per
machine cycle, and most instructions are executed in one to two machine cycles (two
or four CCLK cycles).
RCCLK —
The internal 7.373 MHz RC oscillator output.
PCLK —
Clock for the various peripheral devices and is CCLK/2
8.2.2
CPU clock (CCLK)
The P89LPC904 provides several user-selectable options in generating the CPU
clock. This allows optimization for a range of needs from high precision to lowest
possible cost. These options are configured when the FLASH is programmed and
include an on-chip Watchdog oscillator and an on-chip RC oscillator.
8.3 On-chip RC oscillator option
The P89LPC904 has a 6-bit TRIM register that can be used to tune the frequency of
the RC oscillator. During reset, the TRIM value is initialized to a factory
pre-programmed value to adjust the oscillator frequency to 7.373 MHz,
±
1 % at room
temperature. End-user applications can write to the Trim register to adjust the on-chip
RC oscillator to other frequencies. If CCLK is 8 MHz or slower, the CLKLP SFR bit
(AUXR1.7) can be set to logic 1 to reduce power consumption. On reset, CLKLP is
logic 0 allowing highest performance access. This bit can then be set in software if
CCLK is running at 8 MHz or slower.
8.4 Watchdog oscillator option
The Watchdog has a separate oscillator which has a frequency of 400 kHz. This
oscillator can be used to save power when a high clock frequency is not needed.
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