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參數(shù)資料
| 型號： | P89LPC903FD |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-bit microcontrollers with two-clock 80C51 core 1 kB 3 V Flash with 128-byte RAM |
| 中文描述： | 8-BIT, FLASH, 7.3728 MHz, MICROCONTROLLER, PDSO8 |
| 封裝： | 3.90 MM, PLASTIC, MS-012, SOT-96-1, SO-8 |
| 文件頁數(shù)： | 27/55頁 |
| 文件大小： | 1236K |
| 代理商： | P89LPC903FD |
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Philips Semiconductors
P89LPC901/902/903
8-bit microcontrollers with two-clock 80C51 core
Product data
Rev. 04 — 21 November 2003
27 of 55
9397 750 12293
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
8.6 CPU CLock (CCLK) wake-up delay
The P89LPC901/902/903 has an internal wake-up timer that delays the clock until it
stabilizes depending to the clock source used. If the clock source is any of the three
crystal selections (P89LPC901) the delay is 992 OSCCLK cycles plus 60 to 100
μ
s.
8.7 CPU CLOCK (CCLK) modification: DIVM register
The OSCCLK frequency can be divided down up to 510 times by configuring a
dividing register, DIVM, to generate CCLK. This feature makes it possible to
temporarily run the CPU at a lower rate, reducing power consumption. By dividing the
clock, the CPU can retain the ability to respond to events that would not exit Idle
mode by executing its normal program at a lower rate. This can also allow bypassing
the oscillator start-up time in cases where Power-down mode would otherwise be
used. The value of DIVM may be changed by the program at any time without
interrupting code execution.
8.8 Low power select
The P89LPC901 is designed to run at 12 MHz (CCLK) maximum. However, if CCLK
is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to ‘1’ to lower the power
consumption further. On any reset, CLKLP is ‘0’ allowing highest performance
access. This bit can then be set in software if CCLK is running at 8 MHz or slower.
8.9 Memory organization
The various P89LPC901/902/903 memory spaces are as follows:
DATA
128 bytes of internal data memory space (00h:7Fh) accessed via direct or indirect
addressing, using instruction other than MOVX and MOVC. All or part of the Stack
may be in this area.
SFR
Special Function Registers. Selected CPU registers and peripheral control and
status registers, accessible only via direct addressing.
CODE
64 kB of Code memory space, accessed as part of program execution and via the
MOVC instruction. The P89LPC901/902/903 has 1 kB of on-chip Code memory.
8.10 Data RAM arrangement
The 128 bytes of on-chip RAM is organized as follows:
8.11 Interrupts
The P89LPC901/902/903 uses a four priority level interrupt structure. This allows
great flexibility in controlling the handling of the many interrupt sources.
Table 10:
Type
DATA
On-chip data memory usages
Data RAM
Memory that can be addressed directly and indirectly 128
Size (Bytes)
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| P89LPC907FD | 71-331814-05S |
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| P89LPC907 | 8-bit microcontrollers with two-clock 80C51 core 1 kB 3 V Flash with 128-byte RAM |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| P89LPC903FD,112 | 功能描述:8位微控制器 -MCU 80C51 1K FL 128B RAM RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| P89LPC903FD112 | 制造商:NXP Semiconductors 功能描述:IC 8BIT MCU 80C51 12MHZ SOIC-8 |
| P89LPC904 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:8-bit microcontrollers with two-clock accelerated 80C51 core 1 kB 3 V byte-erasable Flash with 8-bit A/D converter |
| P89LPC904FD | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:8-bit microcontrollers with two-clock accelerated 80C51 core 1 kB 3 V byte-erasable Flash with 8-bit A/D converter |
| P89LPC904FD,529 | 功能描述:8位微控制器 -MCU 1K FL/128B RAM/ADC/STD P/OUT RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
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