參數(shù)資料
型號(hào): P89LPC902FD,112
廠商: NXP Semiconductors
文件頁數(shù): 9/53頁
文件大?。?/td> 0K
描述: IC 80C51 MCU FLASH 1K 8-SOIC
產(chǎn)品培訓(xùn)模塊: Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標(biāo)準(zhǔn)包裝: 1
系列: LPC900
核心處理器: 8051
芯體尺寸: 8-位
速度: 7.3728MHz
外圍設(shè)備: 欠壓檢測/復(fù)位,LED,POR,WDT
輸入/輸出數(shù): 6
程序存儲(chǔ)器容量: 1KB(1K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 2.4 V ~ 3.6 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
包裝: 剪切帶 (CT)
配用: 622-1006-ND - SOCKET ADAPTER BOARD
568-1759-ND - EMULATOR DEBUGGER/PROGRMMR LPC9X
其它名稱: 568-1995-1
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Philips
Semiconductor
s
P89LPC901/902/903
8-bit
micr
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s
with
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loc
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80C51
core
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Philips
Electronics
N.V
.2004.
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Pr
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17
December
2004
17
of
53
[1]
All ports are in input only (high impedance) state after power-up.
[2]
BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is ‘0’. If any are written while BRGEN = 1, the result is unpredictable.
Unimplemented bits in SFRs (labeled ’-’) are X (unknown) at all times. Unless otherwise specied, ones should not be written to these bits since they may be used for other
purposes in future derivatives. The reset values shown for these bits are ‘0’s although they are unknown when read.
[3]
The RSTSRC register reects the cause of the P89LPC901/902/903 reset. Upon a power-up reset, all reset source ags are cleared except POF and BOF; the power-on reset
value is xx110000.
[4]
After reset, the value is 111001x1, i.e., PRE2-PRE0 are all ‘1’, WDRUN = 1 and WDCLK = 1. WDTOF bit is ‘1’ after Watchdog reset and is ‘0’ after power-on reset. Other resets will
not affect WDTOF.
[5]
On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.
[6]
The only reset source that affects these SFRs is power-on reset.
Bit address
8F
8E
8D
8C
8B
8A
89
88
TCON*
Timer 0 and 1 control
88H
TF1
TR1
TF0
TR0
----
00
00000000
TH0
Timer 0 high
8CH
00
00000000
TH1
Timer 1 high
8DH
00
00000000
TL0
Timer 0 low
8AH
00
00000000
TL1
Timer 1 low
8BH
00
00000000
TMOD
Timer 0 and 1 mode
89H
-
T1M1
T1M0
-
T0M1
T0M0
00
00000000
TRIM
Internal oscillator trim register
96H
-
TRIM.5
TRIM.4
TRIM.3
TRIM.2
TRIM.1
TRIM.0
WDCON
Watchdog control register
A7H
PRE2
PRE1
PRE0
-
WDRUN
WDTOF
WDCLK
WDL
Watchdog load
C1H
FF
11111111
WFEED1
Watchdog feed 1
C2H
WFEED2
Watchdog feed 2
C3H
Table 7:
P89LPC901 Special function registers…continued
* indicates SFRs that are bit addressable.
Name
Description
SFR
addr.
Bit functions and addresses
Reset value
MSB
LSB
Hex
Binary
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