參數(shù)資料
型號： P89CE558EBB
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： Single-chip 8-bit microcontroller
中文描述： 8-BIT, FLASH, 16 MHz, MICROCONTROLLER, PQFP80
文件頁數(shù)： 26/72頁
文件大?。?/td> 721K
代理商： P89CE558EBB
Philips Semiconductors
Preliminary specification
P83CE558/P80CE558/P89CE558
Single-chip 8-bit microcontroller
1996 Aug 06
26
Figure 23. Capture control register (CTCON).
7
6
5
4
3
2
1
0
CTCON (E8H)
CTN3
CTP3
CTN2
CTP2
CTN1
CTP1
CTN0
CTP0
Table 18.
Description of CTCON bits
SYMBOL
BIT
FUNCTION
CTN3
CTCON.7
Capture Register 3 triggered by a falling edge on CT3I
CTP3
CTCON.6
Capture Register 3 triggered by a rising edge on CT3I
CTN2
CTCON.5
Capture Register 2 triggered by a falling edge on CT2I
CTP2
CTCON.4
Capture Register 2 triggered by a rising edge on CT2I
CTN1
CTCON.3
Capture Register 1 triggered by a falling edge on CT1I
CTP1
CTCON.2
Capture Register 1 triggered by a rising edge on CT1I
CTN0
CTCON.1
Capture Register 0 triggered by a falling edge on CT0I
CTP0
CTCON.0
Capture Register 0 triggered by a rising edge on CT0I
The contents of the Compare Registers CM0, CM1 and CM2 are
continuously compared with the counter value of Timer T2. When a
match occurs, an interrupt may be invoked. A match of CM0 sets
the bits 0–5 of Port 4, a CM1 match resets these bits and a CM2
match toggles bits 6 and 7 of Port 4, provided these functions are
enabled by the STE respectively RTE registers. A match of CM0
and CM1 at the same time results in resetting bits 0–5 of Port 4.
CM0, CM1 and CM2 are reset by the RSTIN signal.
Figure 24. Interrupt flag register (TM2IR).
7
6
5
4
3
2
1
0
TM2IR (C8H)
T2OV
CMI2
CMI1
CMI0
CTI3
CTI2
CTI1
CTI0
Table 19.
Description of TM2IR bits
SYMBOL
BIT
FUNCTION
T2OV
TM2IR.7
Timer T2 16-bit overflow interrupt flag
CMI2
TM2IR.6
CM2 interrupt flag
CMI1
TM2IR.5
CM1 interrupt flag
CMI0
TM2IR.4
CM0 interrupt flag
CTI3
TM2IR.3
CT3 interrupt flag
CTI2
TM2IR.2
CT2 interrupt flag
CTI1
TM2IR.1
CT1 interrupt flag
CTI0
TM2IR.0
CT0 interrupt flag
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