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參數(shù)資料
| 型號： | P89C662 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 80C51 8-Bit Flash Microcontroller 32KB ISP/IAP FLASH with 1KB RAM(80C51 8位閃速微控制器，帶16KB ISP/IAP閃速存儲器和1KB RAM) |
| 中文描述： | 80C51的8位閃存微控制器具有32KB的ISP /聯(lián)合會與1kB的內(nèi)存（80C51的8位閃速微控制器，帶16KB的供應商/聯(lián)合會閃速存儲器和閃存的1kB的RAM） |
| 文件頁數(shù)： | 52/89頁 |
| 文件大?。?/td> | 490K |
| 代理商： | P89C662 |
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Philips Semiconductors
Product data
P89C660/P89C662/P89C664/
P89C668
80C51 8-bit Flash microcontroller family
16KB/32KB/64KB ISP/IAP Flash with 512B/1KB/2KB/8KB RAM
2002 Oct 28
52
Reduced EMI Mode
The AO bit (AUXR.0) in the AUXR register when set disables the
ALE output.
Reduced EMI Mode
AUXR (8EH)
7
6
5
4
3
2
1
0
–
–
–
–
–
–
EXTRAM
AO
AUXR.1
AUXR.0
EXTRAM
AO
(See more detailed description in
Figure 53.)
Dual DPTR
The dual DPTR structure (see Figure 39) is a way by which the chip
will specify the address of an external data memory location. There
are two 16-bit DPTR registers that address the external memory,
and a single bit called DPS (AUXR1.0), that allows the program
code to switch between them.
New Register Name: AUXR1#
SFR Address: A2H
Reset Value: xxxxx0x0B
AUXR1 (A2H)
7
6
5
4
3
2
1
0
–
–
ENBOOT
–
GF2
0
–
DPS
Where:
DPS (AUXR1.0), enables switching between DPTR0 and DPTR1.
Select Reg
DPS
DPTR0
DPTR1
0
1
The DPS bit status should be saved by software when switching
between DPTR0 and DPTR1.
The GF2 bit is a general purpose user-defined flag. Note that bit 2 is
not writable and is always read as a zero. This allows the DPS bit to
be quickly toggled simply by executing an INC AUXR1 instruction
without affecting the GF2 bit.
The ENBOOT bit determines whether the BOOTROM is enabled
or disabled.
This bit will automatically be set if the status byte is
non zero during reset or PSEN is pulled low, ALE floats high, and
EA > V
IH
on the falling edge of reset. Otherwise, this bit will be
cleared during reset.
DPS
DPTR1
DPTR0
DPH
(83H)
DPL
(82H)
EXTERNAL
DATA
MEMORY
SU00745A
BIT0
AUXR1
Figure 39.
DPTR Instructions
The instructions, that refer to DPTR, refer to the data pointer that is
currently selected by the DPS bit (AUXR1.0). The six instructions
that use the DPTR are as follows:
INC DPTR
Increments the data pointer by 1
MOV DPTR, #data16
Loads the DPTR with a 16-bit constant
MOV A, @ A+DPTR
Move code byte relative to DPTR to ACC
MOVX A, @ DPTR
Move external RAM (16-bit address) to
ACC
MOVX @ DPTR , A
Move ACC to external RAM (16-bit
address)
JMP @ A + DPTR
Jump indirect relative to DPTR
The data pointer can be accessed on a byte-by-byte basis by
specifying the low or high byte in an instruction which accesses the
SFRs. See application note AN458 for more details.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| P89C662HBA | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:80C51 8-bit Flash microcontroller family |
| P89C662HBA/00,512 | 功能描述:IC 80C51 MCU FLASH 32K 44-PLCC RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:89C 產(chǎn)品培訓模塊:MCU Product Line Introduction XMEGA Introduction AVR XMEGA USB Connectivity 標準包裝:90 系列:AVR® XMEGA 核心處理器:AVR 芯體尺寸:8/16-位 速度:32MHz 連通性:I²C，IrDA，SPI，UART/USART 外圍設備:欠壓檢測/復位，DMA，POR，PWM，WDT 輸入/輸出數(shù):50 程序存儲器容量:192KB（96K x 16） 程序存儲器類型:閃存 EEPROM 大小:4K x 8 RAM 容量:16K x 8 電壓 - 電源 (Vcc/Vdd):1.6 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 16x12b; D/A 2x12b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:64-TQFP 包裝:托盤 配用:ATSTK600-RC14-ND - STK600 SOCKET/ADAPTER 64TQFPATSTK600-TQFP64-ND - STK600 SOCKET/ADAPTER 64-TQFPATAVRONEKIT-ND - KIT AVR/AVR32 DEBUGGER/PROGRMMRATAVRISP2-ND - PROGRAMMER AVR IN SYSTEM |
| P89C662HBBD | 制造商: 功能描述: 制造商:undefined 功能描述: |
| P89C662HBBD/00,557 | 制造商:NXP Semiconductors 功能描述: |
| P89C662HFA | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:80C51 8-bit Flash microcontroller family |
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