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參數(shù)資料
| 型號： | P89C662 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 80C51 8-Bit Flash Microcontroller 32KB ISP/IAP FLASH with 1KB RAM(80C51 8位閃速微控制器，帶16KB ISP/IAP閃速存儲器和1KB RAM) |
| 中文描述： | 80C51的8位閃存微控制器具有32KB的ISP /聯(lián)合會與1kB的內(nèi)存（80C51的8位閃速微控制器，帶16KB的供應(yīng)商/聯(lián)合會閃速存儲器和閃存的1kB的RAM） |
| 文件頁數(shù)： | 50/89頁 |
| 文件大小： | 490K |
| 代理商： | P89C662 |
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Philips Semiconductors
Product data
P89C660/P89C662/P89C664/
P89C668
80C51 8-bit Flash microcontroller family
16KB/32KB/64KB ISP/IAP Flash with 512B/1KB/2KB/8KB RAM
2002 Oct 28
50
Interrupt Priority Structure
The P89C660/662/664/668 has an 8 source four-level interrupt
structure (see Table 13).
There are 4 SFRs associated with the four-level interrupt. They are
the IE, IP, IEN1, and IPH (see Figures 35, 36, 37, and 38). The IPH
(Interrupt Priority High) register makes the four-level interrupt
structure possible. The IPH is located at SFR address B7H. The
structure of the IPH register and a description of its bits is shown in
Figure 37.
The function of the IPH SFR, when combined with the IP SFR,
determines the priority of each interrupt. The priority of each
interrupt is determined as shown in the following table:
PRIORITY BITS
INTERRUPT PRIORITY LEVEL
IPH.x
IP.x
0
0
Level 0 (lowest priority)
0
1
Level 1
1
0
Level 2
1
1
Level 3 (highest priority)
The priority scheme for servicing the interrupts is the same as that
for the 80C51, except that there are four interrupt levels rather than
two (as on the 80C51). An interrupt will be serviced as long as an
interrupt of equal or higher priority is not already being serviced. If
an interrupt of equal or higher level priority is being serviced, the
new interrupt will wait until it is finished before being serviced. If a
lower priority level interrupt is being serviced, it will be stopped and
the new interrupt serviced. When the new interrupt is finished, the
lower priority level interrupt that was stopped will be completed.
Table 13.
Interrupt Table
SOURCE
POLLING PRIORITY
REQUEST BITS
HARDWARE CLEAR
N (L)
1
VECTOR ADDRESS
X0
1
IE0
Y (T)
2
03H
SI01 (I
2
C)
2
—
N
2BH
T0
3
TP0
Y
0BH
X1
4
IE1
N (L)
Y (T)
13H
T1
5
TF1
Y
1BH
SP
6
RI, TI
N
23H
T2
7
TF2, EXF2
N
3BH
PCA
8
CF, CCFn
n = 0–4
N
33H
NOTES:
1. L = Level activated
2. T = Transition activated
EX0
IEN0 (0A8H)
Enable Bit = 1 enables the interrupt.
Enable Bit = 0 disables it.
BIT
IEN0.7
SYMBOL
EA
FUNCTION
Global disable bit. If EA = 0, all interrupts are disabled. If EA = 1, each interrupt can be individually
enabled or disabled by setting or clearing its enable bit.
PCA interrupt enable bit
I
2
C interrupt enable bit.
Serial Port interrupt enable bit.
Timer 1 interrupt enable bit.
External interrupt 1 enable bit.
Timer 0 interrupt enable bit.
External interrupt 0 enable bit.
IEN0.6
IEN0.5
IEN0.4
IEN0.3
IEN0.2
IEN0.1
IEN0.0
EC
ES1
ES0
ET1
EX1
ET0
EX0
SU01454
ET0
EX1
ET1
ES0
ES1
EC
EA
0
1
2
3
4
5
6
7
Figure 35. IE Registers
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| P89C662HBA | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:80C51 8-bit Flash microcontroller family |
| P89C662HBA/00,512 | 功能描述:IC 80C51 MCU FLASH 32K 44-PLCC RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:89C 產(chǎn)品培訓(xùn)模塊:MCU Product Line Introduction XMEGA Introduction AVR XMEGA USB Connectivity 標準包裝:90 系列:AVR® XMEGA 核心處理器:AVR 芯體尺寸:8/16-位 速度:32MHz 連通性:I²C，IrDA，SPI，UART/USART 外圍設(shè)備:欠壓檢測/復(fù)位，DMA，POR，PWM，WDT 輸入/輸出數(shù):50 程序存儲器容量:192KB（96K x 16） 程序存儲器類型:閃存 EEPROM 大小:4K x 8 RAM 容量:16K x 8 電壓 - 電源 (Vcc/Vdd):1.6 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 16x12b; D/A 2x12b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:64-TQFP 包裝:托盤 配用:ATSTK600-RC14-ND - STK600 SOCKET/ADAPTER 64TQFPATSTK600-TQFP64-ND - STK600 SOCKET/ADAPTER 64-TQFPATAVRONEKIT-ND - KIT AVR/AVR32 DEBUGGER/PROGRMMRATAVRISP2-ND - PROGRAMMER AVR IN SYSTEM |
| P89C662HBBD | 制造商: 功能描述: 制造商:undefined 功能描述: |
| P89C662HBBD/00,557 | 制造商:NXP Semiconductors 功能描述: |
| P89C662HFA | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:80C51 8-bit Flash microcontroller family |
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