參數(shù)資料
型號(hào): P89C662
廠商: NXP Semiconductors N.V.
英文描述: 80C51 8-Bit Flash Microcontroller 32KB ISP/IAP FLASH with 1KB RAM(80C51 8位閃速微控制器,帶16KB ISP/IAP閃速存儲(chǔ)器和1KB RAM)
中文描述: 80C51的8位閃存微控制器具有32KB的ISP /聯(lián)合會(huì)與1kB的內(nèi)存(80C51的8位閃速微控制器,帶16KB的供應(yīng)商/聯(lián)合會(huì)閃速存儲(chǔ)器和閃存的1kB的RAM)
文件頁(yè)數(shù): 48/89頁(yè)
文件大?。?/td> 490K
代理商: P89C662
Philips Semiconductors
Product data
P89C660/P89C662/P89C664/
P89C668
80C51 8-bit Flash microcontroller family
16KB/32KB/64KB ISP/IAP Flash with 512B/1KB/2KB/8KB RAM
2002 Oct 28
48
S0CON
Address = 98H
Reset Value = 0000 0000B
SM0/FE
7
SM1
6
SM2
5
REN
4
TB8
3
RB8
2
Tl
1
Rl
0
Bit Addressable
(SMOD0 = 0/1)*
Symbol
Function
FE
Framing Error bit. This bit is set by the receiver when an invalid stop bit is detected. The FE bit is not cleared by valid
frames but should be cleared by software. The SMOD0 bit must be set to enable access to the FE bit.
Serial Port Mode Bit 0, (SMOD0 must = 0 to access bit SM0)
Serial Port Mode Bit 1
SM0
SM1
Mode
Description
Baud Rate**
0
0
0
shift register
f
OSC
/6 (6 clock mode) or f
OSC
/12 (12 clock mode)
0
1
1
8-bit UART
variable
1
0
2
9-bit UART
f
OSC
/32 or f
OSC
/16 (6 clock mode) or
f
OSC
/64 or f
OSC
/32 (12 clock mode)
1
1
3
9-bit UART
variable
Enables the Automatic Address Recognition feature in Modes 2 or 3. If SM2 = 1 then Rl will not be set unless the
received 9th data bit (RB8) is 1, indicating an address, and the received byte is a Given or Broadcast Address.
In Mode 1, if SM2 = 1 then Rl will not be activated unless a valid stop bit was received, and the received byte is a
Given or Broadcast Address. In Mode 0, SM2 should be 0.
Enables serial reception. Set by software to enable reception. Clear by software to disable reception.
The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired.
In modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8 is the stop bit that was received.
In Mode 0, RB8 is not used.
Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the
other modes, in any serial transmission. Must be cleared by software.
Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in
the other modes, in any serial reception (except see SM2). Must be cleared by software.
SM0
SM1
SM2
REN
TB8
RB8
Tl
Rl
NOTE:
*SMOD0 is located at PCON6.
**f
OSC
= oscillator frequency
SU01451
Bit:
Figure 32. S0CON: Serial Port Control Register
相關(guān)PDF資料
PDF描述
P89C668HBA 80C51 8-bit Flash microcontroller family 64KB ISP FLASH with 8KB RAM
P89C668HFA 80C51 8-bit Flash microcontroller family 64KB ISP FLASH with 8KB RAM
P89C668 80C51 8-bit Flash microcontroller family 64KB ISP FLASH with 8KB RAM
P89C668HBBD 80C51 8-bit Flash microcontroller family 64KB ISP FLASH with 8KB RAM
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