參數(shù)資料
型號: P87LPC764FN,112
廠商: NXP Semiconductors
文件頁數(shù): 59/60頁
文件大?。?/td> 0K
描述: IC 80C51 MCU 4K OTP 20-DIP
產(chǎn)品培訓(xùn)模塊: Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標(biāo)準(zhǔn)包裝: 18
系列: LPC700
核心處理器: 8051
芯體尺寸: 8-位
速度: 20MHz
連通性: I²C,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,LED,POR,WDT
輸入/輸出數(shù): 18
程序存儲(chǔ)器容量: 4KB(4K x 8)
程序存儲(chǔ)器類型: OTP
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 6 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 20-DIP(0.300",7.62mm)
包裝: 管件
其它名稱: 568-3215-5
935266845112
P87LPC764FN
Philips Semiconductors
Product data
P87LPC764
Low power, low price, low pin count (20 pin)
microcontroller with 4 kbyte OTP
2003 Sep 03
7
SPECIAL FUNCTION REGISTERS
Name
Description
SFR
Address
Bit Functions and Addresses
MSB
LSB
Reset
Value
E7
E6
E5
E4
E3
E2
E1
E0
ACC*
Accumulator
E0h
00h
AUXR1#
Auxiliary Function Register
A2h
KBF
BOD
BOI
LPEP
SRST
0
DPS
02h1
F7
F6
F5
F4
F3
F2
F1
F0
B*
B register
F0h
00h
CMP1#
Comparator 1 control
register
ACh
CE1
CP1
CN1
OE1
CO1
CMF1
00h1
CMP2#
Comparator 2 control
register
ADh
CE2
CP2
CN2
OE2
CO2
CMF2
00h1
DIVM#
CPU clock divide-by-M
control
95h
00h
DPTR:
Data pointer (2 bytes)
DPH
Data pointer high byte
83h
00h
DPL
Data pointer low byte
82h
00h
CF
CE
CD
CC
CB
CA
C9
C8
I2CFG#*
I2C configuration register
C8h/RD
SLAVEN
MASTRQ
0
TIRUN
CT1
CT0
00h1
C8h/WR
SLAVEN
MASTRQ
CLRTI
TIRUN
CT1
CT0
DF
DE
DD
DC
DB
DA
D9
D8
I2CON#*
I2C control register
D8h/RD
RDAT
ATN
DRDY
ARL
STR
STP
MASTER
80h1
D8h/WR
CXA
IDLE
CDR
CARL
CSTR
CSTP
XSTR
XSTP
I2DAT#
I2C data register
D9h/RD
RDAT
0
80h
D9h/WR
XDAT
x
AF
AE
AD
AC
AB
AA
A9
A8
IEN0*
Interrupt enable 0
A8h
EA
EWD
EBO
ES
ET1
EX1
ET0
EX0
00h
EF
EE
ED
EC
EB
EA
E9
E8
IEN1#*
Interrupt enable 1
E8h
ETI
EC1
EC2
EKB
EI2
00h1
BF
BE
BD
BC
BB
BA
B9
B8
IP0*
Interrupt priority 0
B8h
PWD
PBO
PS
PT1
PX1
PT0
PX0
00h1
IP0H#
Interrupt priority 0 high byte
B7h
PWDH
PBOH
PSH
PT1H
PX1H
PT0H
PX0H
00h1
FF
FE
FD
FC
FB
FA
F9
F8
IP1*
Interrupt priority 1
F8h
PTI
PC1
PC2
PKB
PI2
00h1
IP1H#
Interrupt priority 1 high byte
F7h
PTIH
PC1H
PC2H
PKBH
PI2H
00h1
KBI#
Keyboard Interrupt
86h
00h
87
86
85
84
83
82
81
80
P0*
Port 0
80h
T1
CMP1
CMPREF
CIN1A
CIN1B
CIN2A
CIN2B
CMP2
Note 2
97
96
95
94
93
92
91
90
P1*
Port 1
90h
(P1.7)
(P1.6)
RST
INT1
INT0
T0
RxD
TxD
Note 2
A7
A6
A5
A4
A3
A2
A1
A0
P2*
Port 2
A0h
X1
X2
Note 2
P0M1#
Port 0 output mode 1
84h
(P0M1.7)
(P0M1.6)
(P0M1.5)
(P0M1.4)
(P0M1.3)
(P0M1.2)
(P0M1.1)
(P0M1.0)
00h
P0M2#
Port 0 output mode 2
85h
(P0M2.7)
(P0M2.6)
(P0M2.5)
(P0M2.4)
(P0M2.3)
(P0M2.2)
(P0M2.1)
(P0M2.0)
00H
P1M1#
Port 1 output mode 1
91h
(P1M1.7)
(P1M1.6)
(P1M1.4)
(P1M1.1)
(P1M1.0)
00h1
P1M2#
Port 1 output mode 2
92h
(P1M2.7)
(P1M2.6)
(P1M2.4)
(P1M2.1)
(P1M2.0)
00h1
P2M1#
Port 2 output mode 1
A4h
P2S
P1S
P0S
ENCLK
T1OE
T0OE
(P2M1.1)
(P2M1.0)
00h
P2M2#
Port 2 output mode 2
A5h
(P2M2.1)
(P2M2.0)
00h1
PCON
Power control register
87h
SMOD1
SMOD0
BOF
POF
GF1
GF0
PD
IDL
Note 3
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