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參數(shù)資料
| 型號： | P87LPC764FN,112 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 21/60頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC 80C51 MCU 4K OTP 20-DIP |
| 產(chǎn)品培訓(xùn)模塊： | Migrating from 8/16-Bit MCUs to 32-Bit ARMs |
| 標(biāo)準(zhǔn)包裝： | 18 |
| 系列： | LPC700 |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 20MHz |
| 連通性： | I²C，UART/USART |
| 外圍設(shè)備： | 欠壓檢測/復(fù)位，LED，POR，WDT |
| 輸入/輸出數(shù)： | 18 |
| 程序存儲器容量： | 4KB（4K x 8） |
| 程序存儲器類型： | OTP |
| RAM 容量： | 128 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 6 V |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 20-DIP（0.300"，7.62mm） |
| 包裝： | 管件 |
| 其它名稱： | 568-3215-5 935266845112 P87LPC764FN |
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Philips Semiconductors
Product data
P87LPC764
Low power, low price, low pin count (20 pin)
microcontroller with 4 kbyte OTP
2003 Sep 03
27
Low Voltage EPROM Operation
The EPROM array contains some analog circuits that are not
required when VDD is less than 4 V, but are required for a VDD
greater than 4 V. The LPEP bit (AUXR.4), when set by software, will
power down these analog circuits resulting in a reduced supply
current. LPEP is cleared only by power-on reset, so it may be set
ONLY for applications that always operate with VDD less than 4 V.
Reset
The P87LPC764 has an integrated power-on reset circuit which
always provides a reset when power is initially applied to the device.
It is recommended to use the internal reset whenever possible to
save external components and to be able to use pin P1.5 as a
general-purpose input pin.
The P87LPC764 can additionally be configured to use P1.5 as an
external active-low reset pin RST by programming the RPD bit in the
User Configuration Register UCFG1 to 0. The internal reset is still
active on power-up of the device. While the signal on the RST pin is
low, the P87LPC764 is held in reset until the signal goes high.
The watchdog timer on the LPC764 can act as an oscillator fail
detect because it uses an independent, fully on-chip oscillator.
UCFG1 is described in the System Configuration Bytes section of
this datasheet.
SU01169
87LPC764
P1.5
Pin is used as
digital input pin
Internal power-on
Reset active
UCFG1.RPD = 1 (default)
87LPC764
RST
Pin is used as
active-low reset pin
Internal power-on
Reset active
UCFG1.RPD = 0
Figure 20. Using pin P1.5 as general purpose input pin or as low-active reset pin
SU01170
CHIP RESET
CPU
CLOCK
Q
RESET
TIMING
RPD (UCFG1.6)
WDT
MODULE
SOFTWARE RESET
SRST (AUXR1.3)
POWER MONITOR
RESET
RST/VPP PIN
WDTE (UCFG1.7)
S
R
Figure 21. Block Diagram Showing Reset Sources
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