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參數(shù)資料
| 型號： | P87LPC764FN,112 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 24/60頁 |
| 文件大小： | 0K |
| 描述： | IC 80C51 MCU 4K OTP 20-DIP |
| 產(chǎn)品培訓模塊： | Migrating from 8/16-Bit MCUs to 32-Bit ARMs |
| 標準包裝： | 18 |
| 系列： | LPC700 |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 20MHz |
| 連通性： | I²C，UART/USART |
| 外圍設備： | 欠壓檢測/復位，LED，POR，WDT |
| 輸入/輸出數(shù)： | 18 |
| 程序存儲器容量： | 4KB（4K x 8） |
| 程序存儲器類型： | OTP |
| RAM 容量： | 128 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 6 V |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 20-DIP（0.300"，7.62mm） |
| 包裝： | 管件 |
| 其它名稱： | 568-3215-5 935266845112 P87LPC764FN |
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Philips Semiconductors
Product data
P87LPC764
Low power, low price, low pin count (20 pin)
microcontroller with 4 kbyte OTP
2003 Sep 03
29
Mode 0
Putting either Timer into Mode 0 makes it look like an 8048 Timer,
which is an 8-bit Counter with a divide-by-32 prescaler. Figure 24
shows Mode 0 operation.
In this mode, the Timer register is configured as a 13-bit register. As
the count rolls over from all 1s to all 0s, it sets the Timer interrupt
flag TFn. The count input is enabled to the Timer when TRn = 1 and
either GATE = 0 or INTn = 1. (Setting GATE = 1 allows the Timer to
be controlled by external input INTn, to facilitate pulse width
measurements). TRn is a control bit in the Special Function Register
TCON (Figure 23). The GATE bit is in the TMOD register.
The 13-bit register consists of all 8 bits of THn and the lower 5 bits
of TLn. The upper 3 bits of TLn are indeterminate and should be
ignored. Setting the run flag (TRn) does not clear the registers.
Mode 0 operation is the same for Timer 0 and Timer 1. See
Figure 24. There are two different GATE bits, one for Timer 1
(TMOD.7) and one for Timer 0 (TMOD.3).
BIT
SYMBOL
FUNCTION
TCON.7
TF1
Timer 1 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when the
interrupt is processed, or by software.
TCON.6
TR1
Timer 1 Run control bit. Set/cleared by software to turn Timer/Counter 1 on/off.
TCON.5
TF0
Timer 0 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when the
processor vectors to the interrupt routine, or by software.
TCON.4
TR0
Timer 0 Run control bit. Set/cleared by software to turn Timer/Counter 0 on/off.
TCON.3
IE1
Interrupt 1 Edge flag. Set by hardware when external interrupt 1 edge is detected. Cleared by
hardware when the interrupt is processed, or by software.
TCON.2
IT1
Interrupt 1 Type control bit. Set/cleared by software to specify falling edge/low level triggered
external interrupts.
TCON.1
IE0
Interrupt 0 Edge flag. Set by hardware when external interrupt 0 edge is detected. Cleared by
hardware when the interrupt is processed, or by software.
TCON.0
IT0
Interrupt 0 Type control bit. Set/cleared by software to specify falling edge/low level triggered
external interrupts.
IT0
SU01172
IE0
IT1
IE1
TR0
TF0
TR1
TF1
0
1
2
3
4
5
6
7
TCON
Reset Value: 00h
Bit Addressable
Address: 88h
Figure 23. Timer/Counter Control Register (TCON)
SU01173
TLn
(5 BITS)
THn
(8 BITS)
OSC/6
OR
OSC/12
OVERFLOW
Tn PIN
TnOE
TOGGLE
CONTROL
C/T = 1
C/T = 0
Tn PIN
TRn
GATE
INTn PIN
INTERRUPT
TFn
Figure 24. Timer/Counter 0 or 1 in Mode 0 (13-Bit Counter)
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