參數(shù)資料
型號: P87C591SFB
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: Single-chip 8-bit microcontroller with CAN controller
中文描述: 8-BIT, OTPROM, 16 MHz, MICROCONTROLLER, PQFP44
封裝: 10 X 10 X 1.75 MM, PLASTIC, SOT-307-2, QFP-44
文件頁數(shù): 40/161頁
文件大?。?/td> 588K
代理商: P87C591SFB
1999 Aug 19
40
Philips Semiconductors
Objective Specification
Single-chip 8-bit microcontroller with CAN controller
P8xC591
12.5.7
RX I
NTERRUPT
L
EVEL
(RIL)
The RIL register is used to define the receive interrupt level for the RXFIFO. A receive interrupt is generated if the number
of valid CAN message bytes in the RXFIFO exceeds the level specified in this register. Note that receive interrupts are
only generated if complete messages have been received. If RIL is set to 00 the PeliCAN functions like the receive
interrupt behaviour of the SJA1000.
Table 18
Bit interpretation of the Rx Interrupt Level (RIL)
12.5.8
B
US
T
IMING
R
EGISTER
0 (BTR0)
The contents of the Bus Timing Register 0 defines the values of the Baud Rate Prescaler (BRP) and the Synchronization
Jump Width (SJW). This register can be accessed (read/write) if the Reset Mode is active. In Operating Mode, this
register is read only.
Table 19
Bus Timing Register 0 (BTR0) (CAN address 6)
12.5.8.1
Baud Rate Prescaler (BRP)
The period of the CAN system clock t
scl
is programmable and determines the individual bit timing. The CAN system clock
is calculated using the following equation:
12.5.8.2
Synchronization Jump Width (SJW)
To compensate for phase shifts between clock oscillators of different bus controllers, any bus controller must
resynchronize on any relevant signal edge of the current transmission. The synchronization jump width defines the
maximum number of clock cycles a bit period may be shortened or lengthened by one resynchronization:
CAN ADDR. 5
RX INTERRUPT LEVEL (RIL)
7
6
5
4
3
2
1
0
RIL.7
RIL.6
RIL.5
RIL.4
RIL.3
RIL.2
RIL.1
RIL.0
7
6
5
4
3
2
1
0
SJW.1
SJW.0
BRP.5
BRP.4
BRP.3
BRP.2
BRP.1
BRP.0
tscl
tCLK
32
BRP.5
16
BRP.4
8
BRP.3
4
BRP.2
2
BRP.1
BRP.0
1
+
+
×
+
×
+
×
+
×
+
×
(
)
×
=
tCLK
time period of the
μ
C′s system clock
fCLK
------1
=
=
tSJW
tscl
2
SJW.1
SJW.0
1
+
+
×
(
)
×
=
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