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參數(shù)資料
| 型號(hào)： | P87C380 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc(帶DDC接口，同步監(jiān)測(cè)和同步處理的監(jiān)視器微控制器) |
| 中文描述： | 8-BIT, OTPROM, 16 MHz, MICROCONTROLLER, PDIP42 |
| 封裝： | 0.600 INCH, PLASTIC, SOT-270-1, SDIP-42 |
| 文件頁數(shù)： | 57/84頁 |
| 文件大小： | 420K |
| 代理商： | P87C380 |
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1997 Dec 12
57
Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC
interface, auto-sync detection and sync proc.
P83Cx80; P87C380
19.2.1
C
LOCK PRESCALER
To reach the required 12 bit accuracy and the reasonable
crystal clock frequency, the line time of 4 consecutive lines
is measured (see Section 19.2.5). Doing so the maximum
crystal clock frequency is:
2
12
f
From the calculation above it is clear that there will be no
overflow if f
clk
is 10 or 12 MHz. However, for a 16 or
24 MHz crystal f
clk
has to be divided by a factor of 2 to get
a correct clock frequency FOSH for the horizontal part of
the mode detection. If f
clk
used is 10, 12 or 16 MHz then
FOSH will be respectively 10, 12 or 8 MHz.
The same holds for the vertical part of the mode detection.
Here the minimum vertical sync frequency f
V(min)
= 40 Hz,
so the maximum clock frequency to avoid overflow in a
12-bit counter, equals:
2
12
f
V(min)
163.84 kHz
=
To get a maximum accuracy without overflow the clock of
the horizontal section FOSH, should be prescaled down to
this value of FOSV. Thus the scale factor should be at
FOSH
)
least:
Take n = 76 as a suitable scale factor as shown in Fig.23.
Table 62
Clock frequencies
19.2.2
H
ORIZONTAL POLARITY CORRECTION
In order to simplify the processing in the following stages,
the HSYNC polarity correction circuit is able to convert the
input sync signals to positive polarity signals in all
situations. However, be aware that this correction is
achieved by the aid of Hpol and Hper signals. Hpol and
Hper are only settled down in several horizontal scanning
lines (61 lines, if f
HSYNC
goes up) or a few milliseconds
(worst case 1.2 ms, if f
HSYNC
becomes inactive) after
power-on or timing mode change.
f
clk
(MHz)
FOSH
(MHz)
FOSV
(MHz)
10
12
16
10
12
8
131.6
157.9
105.3
f
clk
×
------------4
15.36 MHz
=
≤
FOSV
×
≤
n
-163.84 kHz
12
10
3
kHz
×
73.2
=
=
≥
19.2.3
V
ERTICAL POLARITY CORRECTION
The purpose of the vertical polarity correction is similar to
the horizontal polarity correction. However, it takes a
longer time to get the correct result after power-on or a
timing mode change because at least 5 frames are needed
to stabilize Vper from the input sync signals.
19.2.4
V
ERTICAL SYNC SEPARATION
This function will separate the vertical sync out of the
composite sync. To do so the change in polarity during
VSYNC interval can be utilized to extract VSYNC as
shown in Fig.28. The differentiated sync pulse derived
from HSYNC_P is used to reset an 8-bit upcounter.
At
1
4
of the line time the level of the incoming sync at that
moment is clocked into the last D flip-flop. Be aware that
1
4
of the line period equals
1
16
of parameter Hper because
Hper is calculated based on 4 consecutive lines.
Due to the fact that the differentiator reacts upon every
LOW-to-HIGH transition even an interlaced composite
sync will be separated correctly. Note further that the sync
separation is taken from signal HSYNC_P which is
processed by the Horizontal Polarity Correction circuit but
not necessary with the fixed polarity. As a result the
polarity of the separated vertical sync Vsep will vary with
the incoming composite signal, and in case no composite
sync is present the level will be LOW. According to this
algorithm, Vsep will be always
1
4
HSYNC period shift to the
original VSYNC window. The 8-bit counter in Fig.28 is
stopped at its maximum of FFH, otherwise it will start again
from zero which results in a wrong enable pulse for the
D flip-flop.
All kinds of composite sync input shown in Chapter 27 can
be dealt with by this function. There are 6 types of
composite sync waveforms which can be accepted by the
sync processor (see Fig.39).
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