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參數(shù)資料
| 型號(hào)： | P87C380 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc(帶DDC接口，同步監(jiān)測(cè)和同步處理的監(jiān)視器微控制器) |
| 中文描述： | 8-BIT, OTPROM, 16 MHz, MICROCONTROLLER, PDIP42 |
| 封裝： | 0.600 INCH, PLASTIC, SOT-270-1, SDIP-42 |
| 文件頁數(shù)： | 41/84頁 |
| 文件大小： | 420K |
| 代理商： | P87C380 |
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1997 Dec 12
41
Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC
interface, auto-sync detection and sync proc.
P83Cx80; P87C380
17 DISPLAY DATA CHANNEL (DDC) INTERFACE
The monitor typically includes a number of user controls to
set picture size, position, colour balance, brightness and
contrast. Furthermore, to optimize some internal setting for
different display modes, the timing characteristics should
be acquired by the control side. For factory alignment, it is
preferable to store the entire information in a non-volatile
memory to facilitate production automation. Normally,
monitors provide hardware control panels or a keypad to
perform this control. However, it is now popular for these
controls to go to the PC host. Therefore the
communication between monitor and host becomes an
issue. DDC1, DDC2B, DDC2B+ and DDC2AB
(ACCESS.bus) emerge as a standard for monitor
interface.
P83C880 is compliant to DDC1, DDC2B, DDC2B+ and
DDC2AB (ACCESS.bus). They also conform to the
detection sequence defined by VESA and ACCESS.bus
Industry Group and identify the protocol which they are
communicating with.
A transmitter clocked by the incoming VSYNC is dedicated
for DDC1 operation. An I
2
C-bus interface hardware logic
forms the kernel of DDC2B and DDC2AB. An address
pointer, DDCADR (address 9EH), with post increment
capability is employed to serve DDC1, DDC2B, DDC2B+
and DDC2AB modes.
The conceptual block diagram is illustrated in Fig.23.
17.1
Special Function Registers related to the DDC interface
Table 35
SFRs related to the DDC interface
17.1.1
DDC M
ODE
S
TATUS AND
DDC1 C
ONTROL
R
EGISTER
(DDCCON)
Table 36
DDC Mode Status and DDC1 Control Register (address 9DH)
ADDRESS
SFR
REMARKS
9CH
9DH
9EH
9FH
D8H
D9H
DAH
DBH
RAMBUF
DDCCON
DDCADR
DDCDAT
S1CON
S1STA
S1DAT
S1ADR
See Section 7.3.1.
DDCCON, DDCADR and DDCDAT are mainly created for the DDC1 protocol; they are
explained in Sections 17.1.1 to 17.1.3.
One extra I
2
C-bus interface is used to serve DDC2B, DDC2B+ and DDC2AB. Therefore
S1CON, S1STA, S1DAT and S1ADR are just the copies of the corresponding registers
in the general I
2
C-bus interface. Their usage is exactly the same.
7
6
5
4
3
2
1
0
EX_DAT
SWENB
DDC1_int
DDC1enable
SWH_int
M0
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