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參數(shù)資料
| 型號： | P87C380 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc(帶DDC接口，同步監(jiān)測和同步處理的監(jiān)視器微控制器) |
| 中文描述： | 8-BIT, OTPROM, 16 MHz, MICROCONTROLLER, PDIP42 |
| 封裝： | 0.600 INCH, PLASTIC, SOT-270-1, SDIP-42 |
| 文件頁數(shù)： | 36/84頁 |
| 文件大?。?/td> | 420K |
| 代理商： | P87C380 |
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1997 Dec 12
36
Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC
interface, auto-sync detection and sync proc.
P83Cx80; P87C380
15 ANALOG-TO-DIGITAL CONVERTER (ADC)
The ADC inputs ADC0 and ADC1 share the same pins as
port lines P3.2 and P3.3 respectively. Selection of the pin
function as either an ADC input or as a port line is achieved
using bit ADCE in SFR DFCON (address C0H). When
ADCE = 1, the ADC function is enabled; see Section 7.3.2,
Table 8.
The two channel ADC comprises a 4-bit Digital-to-Analog
Converter (DAC); a comparator; an analog channel
selector and control circuitry. As the digital input to the 4-bit
DAC is loaded by software (a subroutine in the program),
it is known as a software ADC. The block diagram is shown
in Fig.20.
The 4-bit DAC analog output voltage (V
ref
) is determined
by the decimal value of the data held in bits DAC0 to DAC3
(DAC value) of SFR ADCDAT (address C1H). V
ref
is
V
calculated as:
Table 31 lists the V
ref
values as function of DAC3 to DAC0.
When the analog input voltage is higher than V
ref
, the
COMP bit in SFR ADCDAT (address C1H) will be HIGH.
The channel selector, consisting of two analog switches, is
controlled by bit DACHL in SFR ADCDAT; see Table 32.
Table 31
Selection of V
ref
DAC3
DAC2
DAC1
DAC0
V
ref
(V)
1
16
×
V
DD
2
16
×
V
DD
3
16
×
V
DD
4
16
×
V
DD
5
16
×
V
DD
6
16
×
V
DD
7
16
×
V
DD
8
16
×
V
DD
9
16
×
V
DD
10
16
×
V
DD
11
16
×
V
DD
12
16
×
V
DD
13
16
×
V
DD
14
16
×
V
DD
15
16
×
V
DD
V
DD
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
V
ref
--16
DAC value
1
+
(
)
×
=
Table 32
Selection of ADC channel
15.1
Conversion algorithm
There are many algorithms available to achieve the ADC
conversion. The algorithm described below and shown in
Fig.21 uses an iteration process.
1.
Select ADCn channel for conversion. Channel
selection is achieved using bit DACHL, SFR ADCDAT
(address C1H).
2.
Set the digital input to the DAC to 1000. The digital
input to the DAC is selected using bits DAC3 to DAC0
(SFR ADCDAT).
3.
Determine the result of the compare operation. This is
achieved by reading the COMP bit in SFR ADCDAT
using the instruction ‘MOV A, ADCDAT’. If COMP = 1;
the analog input voltage is higher than the reference
voltage (V
ref
). If COMP = 0; the analog input voltage is
lower than the reference voltage (V
ref
).
4.
If COMP = 1; then the analog input voltage is higher
than the reference voltage (V
ref
) and therefore the
digital input to the DAC needs to be increased. Set the
input to the DAC to 1100.
5.
If COMP = 0; then the analog input voltage is lower
than the reference voltage (V
ref
) and therefore the
digital input to the DAC needs to be decreased. Set the
input to the DAC to 0100.
6.
Determine the result of the compare operation by
reading the COMP bit in SFR ADCDAT.
7.
For the DAC = 1100 case.
If COMP = 1; then the analog input voltage is still
greater than V
ref
and therefore the digital input to the
DAC needs to be increased again. Set the input to the
DAC to 1110.
If COMP = 0; then the analog input voltage is now less
than V
ref
and therefore the digital input to the DAC
needs to be decreased. Set the input to the DAC to
1010.
DACHL
CHANNEL SELECTED
0
1
ADC0
ADC1
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