參數(shù)資料
型號： P83C766BDP
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： Microcontrollers for PAL/SECAM TV with OSD and VST
中文描述： 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PDIP42
封裝： 0.600 INCH, PLASTIC, SDIP-42
文件頁數(shù)： 84/92頁
文件大?。?/td> 382K
代理商： P83C766BDP
1
8
P
P
M
w
P
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Notes
1.
A pull-up resistor must be present to prevent a floating input during normal/alternative mode when no external signal is applied to the pad.
Pull-up = present internally.
All ports are in input mode after reset; that means the value at the pin is determined by the external circuitry: pull-up registers Rext (and/or external
applied input).
A pull-up resistor must be present to prevent floating (digital) inputs if the pad is used for the analog inputs ADCO, ADCI and ADC2. This pull-up is
also present if these pins are used as port function. Pull-up is internally.
These pins are standard I/O cells SPF20PGD (2 mA PP slew-rate controlled).
A pull-up resistor must be present to prevent a floating input during nominal/alternative mode when no external signal is applied to the pad.
Pull-up = present internally.
Inverse of the Bp bit (located in OSCON).
After reset the Bp bit (located in OSCON) = 1, therefore output becomes LOW.
Its pull-down resistor is present internally (see Section 13.2).
For the SDIP42 package, pin P1.0 can be exchanged for a V
SS
or V
DD
, pin P1.7 for a V
SS
.
10. For the PLCC68 package, pin P1.0 can be exchanged for a V
DD
line.
11. Output is HIGH via external resistor.
2.
3.
4.
5.
6.
7.
8.
9.
37
37
38
38
39
39
40
40
41
41
42
61
62
62
63
63
64
64
65
65
66
67
68
n.c.
P1.3
INT0
P1.4
T1
P1.5
SCL
P1.6
SDA
P1.7
V
SS
V
SS
V
DD
I/O
I
I/O
I
I/O
I/O
I/O
I/O
I/O
TTL STr
TTL STr
TTL STr
TTL STr
TTL STr
TTL STr
TTL STr
TTL STr
TTL STr
note 9
open-drain
open-drain
open-drain
open-drain
open-drain
open-drain
open-drain + Rpu
(5)
Yes
Yes
Yes
Yes
Yes
Yes
Yes
original state
original state
original state
HIGH
(11)
original state
HIGH
(11)
original state
Z
(2)
Z
(2)
Z
(2)
Z
(2)
Z
(2)
PIN
SYMBOL
TYPE
INPUT LEVEL
OUTPUT TYPE
SLOPE
CONTROL
OUTPUT IN
IDLE MODE
OUTPUT
AFTER RESET
ACTIVE STATE
SW CONTROL
SDIP42 PLCC68
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