參數(shù)資料
型號(hào)： P83C661X2
英文描述： 80C51 8-bit microcontroller family 16KB OTP/ROM. 512B RAM low voltage (2.7 to 5.5 V). low power. high speed (30/33 MHZ). two 400KB I2C interfaces
中文描述： 80C51的8位單片機(jī)系列16KB的檢察官辦公室/光盤。 512B RAM的低電壓（2.7至5.5 V）。低功耗。高速（三十三分之三十兆赫）。 2 400KB I2C接口
文件頁(yè)數(shù)： 77/102頁(yè)
文件大?。?/td> 568K
代理商： P83C661X2
Philips Semiconductors
Product data
P8xC660X2/661X2
80C51 8-bit microcontroller family
16 KB OTP/ROM, 512B
RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33
MHz), two 400KB I
2
C interfaces
2003 Oct 02
77
HARDWARE WATCHDOG TIMER (ONE-TIME
ENABLED WITH RESET-OUT FOR P8XC66xX2)
The WDT is intended as a recovery method in situations where the
CPU may be subjected to software upset. The WDT consists of a
14-bit counter and the WatchDog Timer reset (WDTRST) SFR. The
WDT is disabled at reset. To enable the WDT, the user must write
01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H.
When the WDT is enabled, it will increment every machine cycle
while the oscillator is running and there is no way to disable the
WDT except through reset (either hardware reset or WDT overflow
reset). When the WDT overflows, it will drive an output reset HIGH
pulse at the RST-pin (see the note below).
Using the WDT
To enable the WDT, the user must write 01EH and 0E1H in sequence
to the WDTRST, SFR location 0A6H. When the WDT is enabled, the
user needs to service it by writing 01EH and 0E1H to WDTRST to
avoid a WDT overflow. The 14-bit counter overflows when it reaches
16383 (3FFFH) and this will reset the device. When the WDT is
enabled, it will increment every machine cycle while the oscillator is
running. This means the user must reset the WDT at least every
16383 machine cycles. To reset the WDT, the user must write 01EH
and 0E1H to WDTRST. WDTRST is a write only register. The WDT
counter cannot be read or written. When the WDT overflows, it will
generate an output RESET pulse at the reset pin (see note below).
The RESET pulse duration is 98
×
T
OSC
(6-clock mode; 196 in
12-clock mode), where T
OSC
= 1/f
OSC
. To make the best use of the
WDT, it should be serviced in those sections of code that will
periodically be executed within the time required to prevent a WDT
reset.
相關(guān)PDF資料
PDF描述
P83C660X2 80C51 8-bit microcontroller family 16KB OTP/ROM. 512B RAM low voltage (2.7 to 5.5 V). low power. high speed (30/33 MHZ). two 400KB I2C interfaces
P87C660X2 80C51 8-bit microcontroller family 16KB OTP/ROM. 512B RAM low voltage (2.7 to 5.5 V). low power. high speed (30/33 MHZ). two 400KB I2C interfaces
P87C661X2 80C51 8-bit microcontroller family 16KB OTP/ROM. 512B RAM low voltage (2.7 to 5.5 V). low power. high speed (30/33 MHZ). two 400KB I2C interfaces
P83C748EBPN 80C51 8-bit microcontroller family 2K/64 OTP/ROM, low pin count
P83C748EBAA 80C51 8-bit microcontroller family 2K/64 OTP/ROM, low pin count
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
P83C661X2BBD 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:80C51 8-bit microcontroller family
P83C661X2FA 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:80C51 8-bit microcontroller family
P83C748EBAA 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:80C51 8-bit microcontroller family 2K/64 OTP/ROM, low pin count
P83C748EBDDB 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:80C51 8-bit microcontroller family 2K/64 OTP/ROM, low pin count
P83C748EBPN 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:80C51 8-bit microcontroller family 2K/64 OTP/ROM, low pin count
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