參數(shù)資料
型號(hào)： P83C661X2
英文描述： 80C51 8-bit microcontroller family 16KB OTP/ROM. 512B RAM low voltage (2.7 to 5.5 V). low power. high speed (30/33 MHZ). two 400KB I2C interfaces
中文描述： 80C51的8位單片機(jī)系列16KB的檢察官辦公室/光盤(pán)。 512B RAM的低電壓（2.7至5.5 V）。低功耗。高速（三十三分之三十兆赫）。 2 400KB I2C接口
文件頁(yè)數(shù)： 11/102頁(yè)
文件大小： 568K
代理商： P83C661X2
Philips Semiconductors
Product data
P8xC660X2/661X2
80C51 8-bit microcontroller family
16 KB OTP/ROM, 512B
RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33
MHz), two 400KB I
2
C interfaces
2003 Oct 02
11
CLOCK CONTROL REGISTER (CKCON)
This device allows control of the 6-clock/12-clock mode by means of
both an SFR bit (X2) and an OTP bit. The OTP clock control bit
OX2, when programmed by a parallel programmer (6-clock mode),
supersedes the X2 bit (CKCON.0). The CKCON register is shown
below in Figure 1.
X2
BIT
CKCON.7
CKCON.6
CKCON.5
CKCON.4
CKCON.3
CKCON.2
CKCON.1
CKCON.0
SYMBOL
–
FUNCTION
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
CPU clock; 1 = 6 clocks for each machine cycle, 0 = 12 clocks for each machine cycle
X2
SU01689
–
–
Not Bit Addressable
CKCON
Address = 8Fh
Reset Value =
x0000000B
7
6
5
4
3
2
1
0
–
–
–
–
–
Figure 1. Clock control (CKCON) register
Also please note that the clock divider applies to the serial port for
modes 0 & 2 (fixed baud rate modes). This is because modes 1 & 3
(variable baud rate modes) use either Timer 1 or Timer 2.
Below is the truth table for the CPU clock mode.
Table 1.
OX2 clock mode bit
(can only be set by
parallel programmer)
X2 bit
(CKCON.0)
CPU clock mode
erased
0
12-clock mode
(default)
erased
1
6-clock mode
programmed
X
6-clock mode
RESET
A reset is accomplished by holding the RST pin HIGH for at least
two machine cycles (12 oscillator periods in 6-clock mode, or
24 oscillator periods in 12-clock mode), while the oscillator is running.
To ensure a good power-on reset, the RST pin must be HIGH long
enough to allow the oscillator time to start up (normally a few
milliseconds) plus two machine cycles. At power-on, the voltage on
V
CC
and RST must come up at the same time for a proper start-up.
Ports 1, 2, and 3 will asynchronously be driven to their reset
condition when a voltage above V
IH1
(min.) is applied to RST.
The value on the EA pin is latched when RST is deasserted and has
no further effect.
相關(guān)PDF資料
PDF描述
P83C660X2 80C51 8-bit microcontroller family 16KB OTP/ROM. 512B RAM low voltage (2.7 to 5.5 V). low power. high speed (30/33 MHZ). two 400KB I2C interfaces
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