參數(shù)資料
型號： P83C654X2
廠商： NXP Semiconductors N.V.
英文描述： 80C51 8-bit microcontroller family 16 kB OTP/ROM, 256B RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
中文描述： 80C51的8位單片機系列16kB的檢察官辦公室/光盤，256B的RAM，低電壓（2.7至5.5 V），低功耗，高速（三十三分之三十〇兆赫）
文件頁數(shù)： 68/88頁
文件大?。?/td> 497K
代理商： P83C654X2
Philips Semiconductors
Product data
P83C654X2/P87C654X2
80C51 8-bit microcontroller family
16 kB OTP/ROM,
256B RAM, low voltage (2.7 to 5.5 V), low power, high speed
(30/33 MHz)
2004 Apr 20
68
DC ELECTRICAL CHARACTERISTICS
T
amb
= 0
°
C to +70
°
C or –40
°
C to +85
°
C;
V
CC
= 5 V
±
10 %
; V
SS
= 0 V (30/33 MHz max. CPU clock)
SYMBOL
PARAMETER
TEST
CONDITIONS
LIMITS
UNIT
MIN
TYP
1
MAX
V
IL
V
IH
V
IH1
V
OL
V
OL1
V
OH
V
OH1
Input LOW voltage
11
Input HIGH voltage (ports 0, 1, 2, 3, EA)
Input HIGH voltage, XTAL1, RST
11
Output LOW voltage, ports 1, 2, 3
8
Output LOW voltage, port 0, ALE, PSEN
7, 8
Output HIGH voltage, ports 1, 2, 3
3
Output HIGH voltage (port 0 in external bus
mode), ALE
9
, PSEN
3
Logical 0 input current, ports 1, 2, 3
Logical 1-to-0 transition current, ports 1, 2, 3
6
Input leakage current, port 0
Power supply current
Active mode (see Note 5)
4.5 V < V
CC
< 5.5 V
–0.5
0.2V
CC
+ 0.9
0.7V
CC
–
–
V
CC
– 0.7
V
CC
– 0.7
0.2V
CC
– 0.1
V
CC
+ 0.5
V
CC
+ 0.5
0.4
0.4
–
–
V
V
V
V
V
V
V
V
CC
= 4.5 V; I
OL
= 1.6 mA
2
V
CC
= 4.5 V; I
OL
= 3.2 mA
2
V
CC
= 4.5 V; I
OH
= –30 A
V
CC
= 4.5 V; I
OH
= –3.2 mA
I
IL
I
TL
I
LI
I
CC
V
IN
= 0.4 V
V
IN
= 2.0 V; See note 4
0.45 < V
IN
< V
CC
– 0.3
–1
–
–
–50
–650
±
10
A
A
A
Idle mode (see Note 5)
Power-down mode or clock stopped
(see Figure 54 for conditions)
T
amb
= 0
°
C to 70
°
C
2
30
A
T
amb
= –40
°
C to +85
°
C
3
50
A
V
RAM
R
RST
C
IO
RAM keep-alive voltage
Internal reset pull-down resistor
Pin capacitance
10
(except EA)
1.2
40
–
V
k
pF
225
15
NOTES:
1. Typical ratings are not guaranteed. The values listed are at room temperature, 5 V.
2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V
s of ALE and ports 1 and 3. The noise is due
to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100 pF), the noise pulse on the ALE pin may exceed 0.8 V. In such cases, it may be desirable to qualify
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. I
OL
can exceed these conditions provided that no
single output sinks more than 5 mA and no more than two outputs exceed the test conditions.
3. Capacitive loading on ports 0 and 2 may cause the V
OH
on ALE and PSEN to momentarily fall below the V
CC
–0.7 specification when the
address bits are stabilizing.
4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its
maximum value when V
IN
is approximately 2 V.
5. See Figures 51 through 54 for I
CC
test conditions and Figure 49 for I
CC
vs. Frequency.
12-clock mode characteristics:
Active mode (operating):
I
CC
= 1.0 mA + 1.1 mA
×
FREQ.[MHz]
Active mode (reset):
I
CC
= 7.0 mA + 0.6 mA
FREQ.[MHz]
Idle mode:
I
= 1.0 mA + 0.22 mA
FREQ.[MHz]
6. This value applies to T
= 0
°
C to +70
°
C. For T
= –40
°
C to +85
°
C, I
= –750
μΑ
.
7. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF.
8. Under steady state (non-transient) conditions, I
must be externally limited as follows:
Maximum I
OL
per port pin:
15 mA (*NOTE: This is 85
°
C specification.)
Maximum I
OL
per 8-bit port:
26 mA
Maximum total I
OL
for all outputs:
71 mA
If I
OL
exceeds the test condition, V
OL
may exceed the related specification. Pins are not guaranteed to sink current greater than the listed
test conditions.
9. ALE is tested to V
OH1
, except when ALE is off then V
OH
is the voltage specification.
10.Pin capacitance is characterized but not tested. Pin capacitance is less than 25 pF. Pin capacitance of ceramic package is less than 15 pF
(except EA is 25 pF).
11. To improve noise rejection a nominal 100 ns glitch rejection circuitry has been added to the RST pin, and a nominal 15 ns glitch rejection
circuitry has been added to the INT0 and INT1 pins. Previous devices provided only an inherent 5 ns of glitch rejection.
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