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參數(shù)資料
| 型號： | P83C592 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 8-bit microcontroller with on-chip CAN |
| 中文描述： | 8位微控制器芯片的CAN |
| 文件頁數(shù)： | 35/108頁 |
| 文件大小： | 650K |
| 代理商： | P83C592 |
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1996 Jun 27
35
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xC592
13.5.4
C
OMMAND
R
EGISTER
(CMR)
A command bit initiates an action within the transfer layer of the CAN-controller. The Command Register appears to the
CPU as a read/write memory, except for the bits CMR.0 (TR) to CMR.3 (COS), which return a HIGH if being read.
Table 33
Command Register (address 1)
Table 34
Description of the CMR bits
7
6
5
4
3
2
1
0
RX0A
RX1A
WUM
SLP
COS
RRB
AT
TR
BIT SYMBOL
FUNCTION
7
6
5
RX0A
RX1A
WUM
RX0 Active
. See Table 35; note 1.
RX1 Active
. See Table 35; note 1.
Wake-up Mode
(note 2). If the value of WUM is:
HIGH (single ended), then the difference of the RX signals to the internal reference voltage
1
2
AV
DD
is used for wake up.
LOW (differential), then the differential signal between RX0 and RX1 is used for wake up.
Sleep
(note 3). If the value of SLP is:
HIGH (sleep), then the CAN-controller enters sleep mode if no CAN interrupt is pending and there
is no bus activity.
LOW (wake up), then the CAN-controller functions normally.
Clear Overrun Status
(note 4). If the value of COS is:
HIGH (clear), then the Data Overrun status bit is set to LOW (see Table 37).
LOW (no action), then there is no action.
Release Receive Buffer
(note 5). If the value of RRB is:
HIGH (released), then the Receive Buffer attached to the CPU is released.
LOW (no action), then there is no action.
Abort Transmission
(note 6). If the value of AT is:
HIGH (present) and if not already in progress, a pending Transmission Request is cancelled.
LOW (absent), then there is no action.
Transmission Request
(note 7). If the value of TR is:
HIGH (present), then a message shall be transmitted.
LOW (absent), then there is no action.
4
SLP
3
COS
2
RRB
1
AT
0
TR
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