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參數(shù)資料
| 型號(hào)： | P83C591VFA |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Single-chip 8-bit microcontroller with CAN controller |
| 中文描述： | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQCC44 |
| 封裝： | PLASTIC, MO-047AC, SOT-187-2, LCC-44 |
| 文件頁(yè)數(shù)： | 39/161頁(yè) |
| 文件大?。?/td> | 588K |
| 代理商： | P83C591VFA |
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1999 Aug 19
39
Philips Semiconductors
Objective Specification
Single-chip 8-bit microcontroller with CAN controller
P8xC591
Notes to Table
16
:
1.
A Wake-Up Interrupt is also generated, if the CPU tries to set the Sleep bit while the CAN controller is involved in bus
activities or a CAN Interrupt is pending.
2.
In order to support high priority messages, the Receive Interrupt is forced immediately upon a received message,
which has passed successfully an acceptance filter with high priority (see acceptance filter section). As long as only
messages are received via low priority acceptance filters, the receive interrupt is not forced until the FIFO is filled
with more bytes than programmed in the Rx Interrupt Level Register.
The Receive Interrupt Bit is not cleared upon a read access to the Interrupt Register. Giving the Command “Release
Receive Buffer” will clear RI temporarily. If there is another message available within the FIFO after the release
command, RI is set again. Otherwise RI keeps cleared.
12.5.6
I
NTERRUPT
E
NABLE
R
EGISTER
(IER)
The register allows to enable different types of interrupt sources which are signalled to the CPU. The Interrupt Enable
Register appears to the CPU as a read / write memory.
Table 17
Interrupt Enable Register (IER) CAN Addr. 4, bit interpretation
Note
1.
The Receive Interrupt Enable bit has direct influence to the Receive Interrupt Bit and the interrupt output. If RIE is
cleared, the interrupt pin (INT) will become HIGH immediately, if there is no other interrupt pending.
BIT
SYMBOL
NAME
VALUE
FUNCTION
IER.7
BEIE
Bus Error
Interrupt Enable
1 (enabled) If a bus error has been detected, the CAN Controller requests
the respective interrupt.
0 (disabled)
1 (enabled) If the CAN Controller has lost arbitration, the respective
interrupt is requested.
0 (disabled)
1 (enabled) If the error status of the CAN Controller changes from error
active to error passive or vice versa, the respective interrupt is
requested.
0 (disabled)
1 (enabled) If the sleeping CAN controller wakes up, the respective interrupt
is requested.
0 (disabled)
1 (enabled) If the Data Overrun Status bit is set (see Status Register), the
CAN Controller requests the respective interrupt.
0 (disabled)
1 (enabled) If the Error or Bus Status change (see Status Register), the
CAN Controller requests the respective interrupt.
0 (disabled)
1 (enabled) When a message has been successfully transmitted or the
Transmit Buffer is accessible again, (e.g. after an Abort
Transmission command) the CAN Controller requests the
respective interrupt.
0 (disabled)
1 (enabled) When the Receive Buffer Status is ‘full’ the CAN Controller
requests the respective interrupt.
0 (disabled)
IER.6
ALIE
Arbitration Lost
Interrupt Enable
IER.5
EPIE
Error Passive
Interrupt Enable
IER.4
WUIE
Wake-Up
Interrupt Enable;
Note 1
IER.3
DOIE
Data Overrun
Interrupt Enable
IER.2
EIE
Error Interrupt
Enable
IER.1
TIE
Transmit Interrupt
Enable2
IER.0
RIE
Receive Interrupt
Enable; Note 1
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