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參數(shù)資料
| 型號： | P83C591 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Single-chip 8-bit microcontroller with CAN controller |
| 中文描述： | 單芯片8 - CAN控制器位微控制器 |
| 文件頁數(shù)： | 37/161頁 |
| 文件大?。?/td> | 588K |
| 代理商： | P83C591 |
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1999 Aug 19
37
Philips Semiconductors
Objective Specification
Single-chip 8-bit microcontroller with CAN controller
P8xC591
Notes to Table
15
:
1.
When the Transmit Error Counter exceeds the limit of 255, the Bus Status bit is set ‘1’ (Bus-Off), the CAN Controller
will set the Reset Mode bit ‘1’ (present), an Error Warning and a Bus Error Interrupt is generated, if enabled. The
Receive Error Counter is set to ‘127’. It will stay in this mode until the CPU clears the Reset Request bit. Once this
is completed the CAN Controller will wait the minimum protocol-defined time (128 occurrences of the Bus-Free
signal) counting down the Receive Error Counter. After that the Bus Status bit is cleared (Bus-On), the Error Status
bit is set ‘0’ (ok), the Error Counters are reset and an Error Interrupt is generated, if enabled. Reading the RX Error
Counter during this time gives information about the status of the Bus-Off recovery.
2.
Errors detected during reception or transmission will effect the error counters according to the CAN specification. The
Error Status bit is set when at least one of the error counters has reached or exceeded the CPU warning limit of 96.
An Error Interrupt is generated, if enabled.
3.
If both the Receive Status and the Transmit Status bits are ‘0’ (idle) the CAN-Bus is idle.
4.
The Transmission Complete Status bit is set ‘0’ (incomplete) whenever the Transmission Request bit or the Self
Reception Request bit is set ‘1’. The Transmission Complete Status bit will remain ‘0’ until a message is transmitted
successfully.
5.
If the CPU tries to write to the Transmit Buffer when the Transmit Buffer Status bit is ‘0’ (locked), the written byte will
not be accepted and will be lost without this being signalled.
6.
After reading all messages within the RXFIFO and releasing their memory space with the command Release Receive
Buffer this bit is cleared.
7.
After reading all messages within the RXFIFO and releasing their memory space with the command Release Receive
Buffer this bit is cleared.
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