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| 型號(hào)： | P83C591 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Single-chip 8-bit microcontroller with CAN controller |
| 中文描述： | 單芯片8 - CAN控制器位微控制器 |
| 文件頁(yè)數(shù)： | 34/161頁(yè) |
| 文件大?。?/td> | 588K |
| 代理商： | P83C591 |
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1999 Aug 19
34
Philips Semiconductors
Objective Specification
Single-chip 8-bit microcontroller with CAN controller
P8xC591
12.5.2
M
ODE
R
EGISTER
(MOD)
The contents of the Mode Register are used to change the behaviour of the CAN Controller. Bits may be set or reset by
the CPU that uses the Mode Register as a read / write memory. Reserved Bits are read as “0”.
Table 13
Mode Register (MOD) CAN Addr. 0 bit interpretation
Notes
1.
A write access to the bits MOD.1, MOD.2, MOD.5, MOD.6 and MOD.7 is possible only, if the Reset Mode is entered
previously.
The PeliCAN Block will enter Sleep Mode, if the Sleep Mode bit is set ‘1’ (sleep), there is no bus activity and no
interrupt is pending. Setting of SM with at least one of the previously mentioned exceptions valid will result in a
wake-up interrupt. The CAN block will wake up if SM is set LOW (wake-up) or there is bus activity. On wake-up, a
Wake-up Interrupt is generated. A sleeping CAN block which wakes up due to bus activity will not be able to receive
this message until it detects 11 consecutive recessive bits (Bus-Free sequence). Note that setting of SM is not
possible in Reset Mode. After clearing of Reset Mode, setting of SM is possible first, when Bus-Free is detected
again.
2.
BIT
SYMBOL
NAME
VALUE
FUNCTION
MOD.7
TM
Test Mode;
Note 1
1 (activated)
The TX0 pin will reflect the bit, detected on RX pin, with the
next positive edge of the system clock. TN0 and TP0 are
configured according the setting of OCR. The TXDC output
directly reflects RXDC. The RPM bit has no influence within
this mode.
0 (disabled)
1 (high active)
MOD.6
MOD.5
RIPM
RPM
Reserved.
Receive Polarity
Mode
RXD inputs are active high (dominant = 1).
0 (low active)
1 (high active)) The PeliCAN Block enters Sleep Mode if no CAN interrupt is
pending and there is no bus activity.
0 (low active)
1 (self test)
In this mode a full node test is possible without any other
active node on the bus using the Self Reception Request
command. The CAN Controller will perform a successful
transmission, even if there is no acknowledge received.
0 (normal)
An acknowledge is required for successful transmission.
1 (reset)
In this mode the CAN would give no acknowledge to the
CAN bus, even if a message is received successfully. No
active error flags are driven to the bus. The error counters
are stopped at the current value.
0 (normal)
Normal communication.
1 (reset)
Setting the Reset Mode bit results in aborting the current
transmission/reception of a message and entering the Reset
Mode.
0 (normal)
On the’1’-to-’0’ transition of the Reset Mode bit, the CAN
Controller returns to the Operating Mode.
RXD inputs are active low (dominant = 0).
MOD.4
SM
Sleep Mode;
Note 2
MOD.3
MOD.2
reserved
Self Test Mode;
Note 1
STM
MOD.1
LOM
Listen Only
Mode; Notes 1
and 3
MOD.0
RM
Reset Mode;
Note 4
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