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參數(shù)資料
| 型號(hào)： | P83C524 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 8-bit microcontrollers |
| 中文描述： | 8位微控制器 |
| 文件頁數(shù)： | 29/76頁 |
| 文件大?。?/td> | 400K |
| 代理商： | P83C524 |
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1997 Dec 15
29
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
11.3
Watchdog Timer T3
The Watchdog Timer (WDT) see Fig.17, consists of an
11-bit prescaler and an 8-bit timer formed by SFR T3. The
prescaler is incremented by an on-chip oscillator with a
fixed frequency of 1 MHz. The maximum tolerance on this
frequency is
50% and +100%. The 8-bit timer increments
every 2048 cycles of the on-chip oscillator. When a timer
overflow occurs, the microcontroller is reset and a
reset-output-pulse of 16 x 2048 cycles of the on-chip
oscillator is generated at pin RST. The internal RESET
signal is not inhibited when the external RST pin is kept
LOW by e.g. an external reset circuit. The RESET signal
drives Ports 1, 2 and 3 outputs into the High state and Port
0 into high impedance, no matter if the XTAL-clock is
running or not.
The WDT is controlled by WDCON SFR with the direct
address location A5H. WDCON can be read and written by
software. A value of A5H in WDCON halts the on-chip
oscillator and clears both the prescaler and Timer T3. After
RESET, WDCON contains A5H. Every value other than
A5H in WDCON enables the WDT. When the WDT is
enabled it runs independent of the XTAL-clock.
Timer T3 can be read on the fly. Timer T3 can be written
only if WDCON has previously been loaded with 5AH,
otherwise T3 and the prescaler are not affected. A
successful write operation to T3 also clears the prescaler
and clears WDCON. During a read or write operation
addressing T3, the output of the on-chip oscillator is
inhibited to prevent timing problems due to asynchronous
increments of T3. To prevent an overflow of the WDT, the
user program has to reload T3 within periods that are
shorter than the programmed Watchdog time interval. This
time interval is determined by the 8-bit reload value that is
written into register T3.
The advantages of this implementation are:
Only an internal reset connection to the microcontroller
core
The Power-down mode and the Watchdog (WDT)
function can be used concurrently
The WDT also monitors the XTAL oscillator. In case of a
failure the port outputs are forced to a defined High state
Interference will not disable the WDT because it is
unlikely that it will force WDCON to A5H
Tolerances of the on-chip oscillator can be adjusted by
testing the T3 value and adapting the reload value
The WDT can be enabled and disabled under control of
the user software. This gives the possibility to use both
the Watchdog function and the Power-down function
The direct address A5H of WDCON and its disable value
A5H will not unintentionally be present at a random
location in the field of program code, except for
immediate data, because the opcode A5H is not used in
the instruction set.
Watchdog time interval
T3
)
(
–
]
2048
×
on-chip oscillator frequency
---------256
=
Fig.17 Watchdog Timer T3.
handbook, full pagewidth
MBC471 - 1
8 - BIT TIMER
T3
11 - BIT
PRESCALER
WDCON
clear
input
A5H
5AH
clear
ON - CHIP -
OSCILLATOR
halt
write
read
clear
WR - T3
RD - T3
over-flow
VDD
VSS
internal
RESET
RST
this signal is active if WDCON
contains this hex value
IBS
RRST
(1)
(1)
(1)
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