參數(shù)資料
型號(hào)： P83C524
廠商： NXP Semiconductors N.V.
英文描述： 8-bit microcontrollers
中文描述： 8位微控制器
文件頁數(shù)： 22/76頁
文件大小： 400K
代理商： P83C524
1997 Dec 15
22
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
10 I/O FACILITIES
The P83C528 has four 8-bit ports. Ports 0-3 are the same
as in the 80C51, with the exception of the additional
function of Port 1. Port lines P1.0 and P1.1 may be used
as inputs for Timer 2, P1.1 may also be used as an
additional (third) external interrupt request input. Port lines
P1.6 and P1.7 may be selected as the SCL and SDA lines
of Serial Port SIO1 (I
2
C). Because the I
2
C-bus may be
active while the device is disconnected from V
DD
, these
pins are provided with open drain drivers. Pins P1.6 and
P1.7 do not have pull-up devices when used as ports.
Ports 0, 1, 2, and 3 perform the following alternative
functions:
Port 0: provides the multiplexed low-order address and
data bus used for expanding the P83C528 with standard
memories and peripherals.
Port 1: pins can be configured individually to provide:
external interrupt request input (external interrupt 2);
external inputs for Timer/counter 2; SCL and SDA for
the I
2
C interface.
Port 2: provides the high-order address bus when
expanding the P83C528 with external program memory
and/or external data memory.
Port 3: pins can be configured individually to provide:
external interrupt request inputs (external interrupt 0/1);
external inputs for Timer/counter 0 and
Timer/counter 1; Serial Port receiver input and
transmitter output control-signals to read and write
external data memory.
Bits which are not used for the alternative functions may be
used as normal bidirectional I/O pins. The generation or
use of a Port 1 or Port 3 pin as an alternative function is
carried out automatically by the P83C528 provided the
associated SFR bit is HIGH. Otherwise the port pin is held
at a logical LOW level.
Fig.13 I/O buffers in the P83C528 (Ports 1, 2 and 3 except P1.6 and P1.7).
handbook, full pagewidth
MLA513
p1
p2
p3
input data
read port pin
2 oscillator
periods
n
strong pull-up
I/O PIN
PORT
+5 V
I1
Q
from port latch
INPUT
BUFFER
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