參數(shù)資料
型號: P83C380
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc(帶DDC接口,同步監(jiān)測和同步處理的監(jiān)視器微控制器)
中文描述: 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PDIP42
封裝: 0.600 INCH, PLASTIC, SOT-270-1, SDIP-42
文件頁數(shù): 62/84頁
文件大?。?/td> 420K
代理商: P83C380
1997 Dec 12
62
Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC
interface, auto-sync detection and sync proc.
P83Cx80; P87C380
The 5-bit down counter is used to generate a pulse with
pulse width t
W(H)
. As shown in Fig.23, the SR flip-flop will
be set by either HPST (free running/missing sync pulse) or
by the leading or trailing edge of the incoming sync pulse,
HSYNC_P. In the same way the SR flip-flop will be reset
by either the end of the incoming sync pulse or by the
pulse width counter.
If necessary (HPG1, HPG0: 1, 1), the substitution pulse
can be suppressed and only the incoming HSYNC pulse
will be delivered out. The frequency of the free running
Hfp
pulse is:
The pulse width of the free running mode is:
t
W(H)
= T
FOSH
×
(HOPW<4:0>)
f
H(free)
FOSH
=
Fig.30 Horizontal pulse generator.
handbook, full pagewidth
MGG039
Q
HSYNC_P
HFP
Hper
HPG1 to HPG0
S
SR-FF
R
Q
HOPW
FOSH
DATA
LOAD
DECISION
PULSE
RISE/FALL
GENERATOR
PULSE
WIDTH
GENERATOR
FOSH
PHSI
DOWN
COUNTER
COMPARATOR
D9..0
L
HPST
HSYNCout
Q9..0
'0'
19.2.8
V
ERTICAL PULSE GENERATOR
The clock used in this vertical pulse generator must be
switchable between FOSV (needed to generate missing
sync pulses) and HPST (free running syncs from the
horizontal pulse generator) needed in the free running
mode. In the latter situation one vertical sync pulse (i.e.
one frame) will be generated by including an integer
number of the horizontal scanning lines (i.e. HPST). In this
case, the pulse width is also counted by HPST. The rest is
more or less equal to the horizontal pulse generator.
The frequency of the free running pulse is:
f
2
Vfp
×
The pulse width of the free running mode is:
t
W(V)
= T
H(free)
×
[(VOPW<3:0>) + 2]
×
2
f
V(free)
------------------
=
19.2.9
C
APTURE REGISTERS
This function captures the 6 parameters, Hper, Hpol,
Hpres, Vper, Vpol and Vpres such that the current value of
these parameters is available for the microcontroller core
(software) at all times. The mode change interrupt will be
activated if:
The horizontal period changes
The vertical period changes
The horizontal polarity changes
The vertical polarity changes.
19.2.10 C
ONTROL
All necessary control signals for the complete hardware
mode detection are mentioned in Section 19.1.
相關(guān)PDF資料
PDF描述
P87C380 Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc(帶DDC接口,同步監(jiān)測和同步處理的監(jiān)視器微控制器)
P83C880 Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc(帶DDC接口,同步監(jiān)測和同步處理的監(jiān)視器微控制器)
P83C180 Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc(帶DDC接口,同步監(jiān)測和同步處理的監(jiān)視器微控制器)
P83C370AAR Microcontrollers for PAL/SECAM TV with OSD and VST(帶 OSD和 VST的在PAL/SECAM TV中應(yīng)用的微控制器)
P83C570AAR Microcontrollers for NTSC TVs with On-Screen Display OSD and Closed Caption CC
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