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參數(shù)資料
| 型號(hào)： | P83C266BDR |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Microcontrollers for PAL/SECAM TV with OSD and VST |
| 中文描述： | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PDIP42 |
| 封裝： | 0.600 INCH, PLASTIC, SDIP-42 |
| 文件頁(yè)數(shù)： | 54/92頁(yè) |
| 文件大小： | 382K |
| 代理商： | P83C266BDR |
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1999 Mar 10
54
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
17.4
OSD clock generator
The clock generator comprises Phase-Locked-Loop circuitry. The frequency of the OSD clock is programmable and is
determined by the decimal value of the contents of the 8-bit OSPLL register. OSD clock frequencies within the range
4 to 12 MHz can be selected in increments of 31.25 kHz. The OSD frequency (f
OSD
) is calculated as shown below:
Where f
HSYNCP
is the horizontal sync frequency after the polarity selection circuit.
17.4.1
OSD PLL R
EGISTER
(OSPLL)
The reset value of OSPLL is 00H.
Table 62
OSD PLL Register (SFR address C4H)
Table 63
Description of OSPLL bits
Table 64
Selection of OSD clock frequency
7
6
5
4
3
2
1
0
PLL7
PLL6
PLL5
PLL4
PLL3
PLL2
PLL1
PLL0
BIT
SYMBOL
DESCRIPTION
7 to 0
PLL7 to PLL0 These 8 bits are used to select the OSD clock frequency. Examples of OSD clock
selection are shown in Table 64.
OSPLL VALUE
OSD FREQUENCY (MHz)
00H
3FH
7FH
BFH
FFH
4.00
6.00
8.00
10.00
12.00
f
OSD
2
f
HSYNCP
129
OSPLL value
+
(
)
×
×
=
Fig.33 OSD PLL.
handbook, halfpage
MGM681
OSPLL
(C4H)
DIVIDER
SYSCLK
÷
2
fOSD
HSYNC
PLL
HSYNCP
LOAD_SFR
RESET
DI
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