參數(shù)資料
型號(hào)： P83C266BDR
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： Microcontrollers for PAL/SECAM TV with OSD and VST
中文描述： 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PDIP42
封裝： 0.600 INCH, PLASTIC, SDIP-42
文件頁(yè)數(shù)： 18/92頁(yè)
文件大小： 382K
代理商： P83C266BDR
1999 Mar 10
18
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
10.3
Table 6
Serial Control Register (S1CON)
Serial Control Register (SFR address D8H)
Table 7
Description of S1CON bits
7
6
5
4
3
2
1
0
CR2
ENS1
STA
STO
SI
AA
CR1
CR0
BIT
SYMBOL
DESCRIPTION
6
ENSI
Enable Serial I/O.
When ENSI = 0, the SIO is disabled and reset. The SDA and SCL
outputs are in a high-impedance state; P1.5 and P1.6 function as open-drain ports.
When ENSI = 1, the SIO is enabled. The P1.5 and P1.6 port latches must be set to
logic 1.
START flag.
When the STA bit is set in Slave mode, the SIO hardware checks the
status of the I
2
C-bus and generates a START condition if the bus is free. If STA is set
while the SIO is in Master mode, SIO transmits a repeated START condition.
STOP flag.
With this bit set while in Master mode a STOP condition is generated. When
a STOP condition is detected on the bus, the SIO hardware clears the STO flag. In the
Slave mode, the STO flag may also be set to recover from an error condition. In this
case, no STOP condition is transmitted to the I
2
C-bus interface. However, the SIO
hardware behaves as if a STOP condition has been received and releases SDA and
SCL. The SIO then switches to the ‘not addressed’ slave receiver mode. The STO flag
is automatically cleared by hardware.
SIO interrupt flag.
When the SI flag is set, an acknowledge is returned after any one of
the following conditions:
A START condition is generated in Master mode
Own slave address received during AA = 1
General call address received while S1ADR.0 = 1 and AA = 1
Data byte received or transmitted in Master mode (even if arbitration is lost)
Data byte received or transmitted as selected slave
STOP or START condition received as selected slave receiver or transmitter.
Assert Acknowledge.
When the AA flag is set, an acknowledge (LOW level to SDA)
will be returned during the acknowledge clock pulse on the SCL line when:
Own slave address is received
General call address is received (S1ADR.0 = 1)
Data byte received while device is programmed as a Master receiver
Data byte received while device is a selected Slave receiver.
With AA = 0, no acknowledge will be returned. Consequently, no interrupt is requested
when the ‘own slave address’ or general call address is received.
Clock Rate selection.
These three bits determine the serial clock frequency when SIO
is in a Master mode; see Table 8. The maximum I
2
C-bus frequency is 400 KHz.
5
STA
4
STO
3
SI
2
AA
7
1
0
CR2
CR1
CR0
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