- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄367723 > P80C591SFA (NXP SEMICONDUCTORS) Single-chip 8-bit microcontroller with CAN controller PDF資料下載
參數(shù)資料
| 型號(hào)： | P80C591SFA |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Single-chip 8-bit microcontroller with CAN controller |
| 中文描述： | 8-BIT, 16 MHz, MICROCONTROLLER, PQCC44 |
| 封裝： | PLASTIC, SOT-187-2, LCC-44 |
| 文件頁(yè)數(shù)： | 47/161頁(yè) |
| 文件大?。?/td> | 588K |
| 代理商： | P80C591SFA |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)當(dāng)前第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)
1999 Aug 19
47
Philips Semiconductors
Objective Specification
Single-chip 8-bit microcontroller with CAN controller
P8xC591
12.5.16 TX E
RROR
C
OUNTER
R
EGISTER
(TXERR)
The TX Error Counter Register reflects the current value of
the Transmit Error Counter. In Operating Mode this
register appears to the CPU as a read only memory. A
write access to this register is possible only in Reset Mode.
After hardware reset this register is initialised to “0”. If a
bus-off event occurs, the TX Error Counter is initialised to
127 to count the minimum protocol-defined time (128
occurrences of the Bus-Free signal). Reading the TX Error
Counter during this time gives information about the status
of the Bus-Off recovery.
If Bus Off is active, a write access to TXERR in the range
of 0 to 254 clears the Bus Off Flag and the controller will
wait for one occurrence of 11 consecutive recessive bits
(bus free) after clearing of Reset Mode.
Writing 255 to TXERR allows to initiate a CPU-driven Bus
Off event. Note, that a CPU-forced content change of the
TX Error Counter is possible only, if the Reset Mode was
entered previously. An Error or Bus Status change (Status
Register), an Error Warning or an Error Passive Interrupt
forced by the new register content will not occur, until the
Reset Mode is cancelled again. After leaving the Reset
Mode, the new TX Counter content is interpreted and the
Bus Off event is performed in the same way, as if it was
forced by a bus error event. That means, that the Reset
Mode is entered again, the TX Error Counter is initialised
to 127, the RX Counter is cleared and all concerned Status
and Interrupt Register Bits are set.
Clearing of Reset Mode now will perform the protocol
defined Bus Off recovery sequence (waiting for 128
occurrences of the Bus-Free signal).
If the Reset Mode is entered again before the end of Bus
Off recovery (TXERR > 0), Bus Off keeps active and
TXERR is frozen.
Table 30
TX Error Counter Register (TXERR) (CAN address 15)
7
6
5
4
3
2
1
0
TXERR.7
TXERR.6
TXERR.5
TXERR.4
TXERR.3
TXERR.2
TXERR.1
TXERR.0
12.5.17 A
CCEPTANCE
F
ILTER
With the help of the Acceptance Filter the CAN Controller
is able to allow passing of received messages to the
RXFIFO only when the identifier bits and the Frame Type
of the received message are equal to the predefined ones
within the Acceptance Filter Registers. If at least one filter
matches, the message is copied to the receive FIFO.
The Acceptance Filter is defined by the Acceptance Code
Registers (ACRn) and the Acceptance Mask Registers
(AMRn). Within the Acceptance Code Registers the bit
patterns of messages to be received are defined. The
corresponding Acceptance Mask Registers allow defining
certain bit positions to be “don‘t care”.
The PeliCAN is designed to support four of so called
Acceptance Filter Banks. Each bank has the functionality
known from the SJA1000 with the extension, that a filter
change is possible “on the fly”. Additionally the used
Frame Format of each filter bank is programmable now.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| P83C591VFB | Single-chip 8-bit microcontroller with CAN controller |
| P87C591VFB | 27 PF 5% 50V NPO/COG (0805) CHIP CAP TR |
| P83C591SFA | Single-chip 8-bit microcontroller with CAN controller |
| P87C591SFA | Single-chip 8-bit microcontroller with CAN controller |
| P80C591SFB | Single-chip 8-bit microcontroller with CAN controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| P80C591SFB | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Single-chip 8-bit microcontroller with CAN controller |
| P80C592 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:8-bit microcontroller with on-chip CAN |
| P80C592FFA | 制造商:NXP Semiconductors 功能描述: |
| P80C592FFA/00,512 | 功能描述:8位微控制器 -MCU 80C51 W/CAN 16MHZ ROMLESS RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| P80C592FFA/00,512 | 制造商:NXP Semiconductors 功能描述:8BIT MCU+CAN, SMD, 80C592, PLCC68 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。