參數(shù)資料
型號: P80C591SFA
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: Single-chip 8-bit microcontroller with CAN controller
中文描述: 8-BIT, 16 MHz, MICROCONTROLLER, PQCC44
封裝: PLASTIC, SOT-187-2, LCC-44
文件頁數(shù): 36/161頁
文件大?。?/td> 588K
代理商: P80C591SFA
1999 Aug 19
36
Philips Semiconductors
Objective Specification
Single-chip 8-bit microcontroller with CAN controller
P8xC591
4.
The Abort Transmission bit is used when the CPU requires the suspension of the previously requested transmission,
e.g. to transmit a more urgent message before. A transmission already in progress is not stopped. In order to see if
the original message had been either transmitted successfully or aborted, the Transmission Complete Status bit
should be checked. This should be done after the Transmit Buffer Status bit has been set ‘1’ or a Transmit Interrupt
has been generated.
If the Transmission Request or the Self Reception Request bit was set ‘1’ in a previous command, it cannot be
cancelled by setting the Transmission Request bit ‘0’. The requested transmission may be cancelled by setting the
Abort Transmission bit ‘1’.
Setting the command bits CMR.0 and CMR.1 simultaneously results in transmitting a message once. No
re-transmission will be performed in case of an error or arbitration lost (single shot transmission). Setting the
command bits CMR.4 and CMR.1 simultaneously results in sending the transmit message once using the self
reception feature. No re-transmission will be performed in case of an error or arbitration lost. Setting the command
bits CMR.0, CMR.1 and CMR.4 simultaneously results in transmitting a message once as described for CMR.0 and
CMR.1. The moment the Transmit Status bit is set within the Status Register, the internal Transmission Request Bit
is cleared automatically. Setting CMR.0 and CMR.4 simultaneously will ignore the set CMR.4 bit.
5.
6.
12.5.4
S
TATUS
R
EGISTER
(SR)
The content of the Status Register reflects the status of the CAN Controller. The Status Register appears to the CPU as
a read only memory.
Table 15
Status Register (SR) CAN Addr. 2, bit interpretation
BIT
SYMBOL
NAME
VALUE
FUNCTION
SR.7
BS
Bus Status; Note 1
1 (Bus-Off)
0 (Bus-On)
1 (error)
The CAN Controller is not involved in bus activities.
The CAN Controller is involved in bus activities
At least one of the error counters has reached or
exceeded the CPU warning limit (96).
Both error counters are below the warning limit.
The CAN Controller is transmitting a message.
SR.6
ES
Error Status; Note 2
0 (ok)
1 (transmit)
0 (idle)
1 (receive)
0 (idle)
1 (complete)
SR.5
TS
Transmit Status;
Note 3
SR.4
RS
Receive Status;
Note 3
The CAN Controller is receiving a message.
SR.3
TCS
Transmission
Complete Status;
Note 4
Last requested transmission has been successfully
completed. Previously requested transmission is not
yet completed
0 (incomplete)
1 (released)
SR.2
TBS
Transmit Buffer
Status; Note 5
The CPU may write a message into the Transmit
Buffer.
The CPU cannot access the Transmit Buffer. A
message is either waiting for transmission or is in
transmitting process.
A message was lost because there was not enough
space for that message in the RXFIFO.
No data overrun has occurred since the last Clear Data
Overrun command was given
One or more complete messages are available in the
RXFIFO.
No message is available.
0 (locked)
SR.1
DOS
Data Overrun
Status; Note 6
1 (overrun)
0 (absent)
SR.0
RBS
Receive Buffer
Status; Note 7
1 (full)
0 (empty)
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