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參數(shù)資料
| 型號(hào)： | P3Z22V10IBDH |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | PLD |
| 英文描述： | 3V zero power, TotalCMOS, universal PLD device |
| 中文描述： | EE PLD, 15 ns, PDSO24 |
| 封裝： | 4.40 MM, PLASTIC, SOT-355-1, TSSOP-24 |
| 文件頁(yè)數(shù)： | 6/16頁(yè) |
| 文件大?。?/td> | 191K |
| 代理商： | P3Z22V10IBDH |
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Philips Semiconductors
Product specification
P3Z22V10
3V zero power, TotalCMOS
, universal PLD device
1997 Jul 18
6
F
0
1
1
0
0
1
0
0
1
CLK
1
AR
SP
S
1
S
0
S
1
S
0
OUTPUT CONFIGURATION
0 = Unprogrammed fuse
1 = Programmed fuse
D
Q
Q
0
0
1
1
0
1
0
1
Registered/Active-LOW/Macrocell feedback
Registered/Active-HIGH/Macrocell feedback
Combinatorial/Active-LOW/Pin feedback
Combinatorial/Active-HIGH/Pin feedback
SP00484
Figure 2.
Output Macro Cell Logic Diagram
F
CLK
AR
SP
S
0
= 0
S
1
= 0
D
Q
Q
a. Registered/Active-LOW
F
CLK
AR
SP
S
0
= 1
S
1
= 0
D
Q
Q
b. Registered/Active-HIGH
F
S
0
= 0
S
1
= 1
c. Combinatorial/Active-LOW
d. Combinatorial/Active-HIGH
F
S
0
= 1
S
1
= 1
SP00376
Figure 3.
Output Macro Cell Configurations
Programmable I/O Macrocell
The output macrocell provides complete control over the
architecture of each output. the ability to configure each output
independently permits users to tailor the configuration of the
P3Z22V10 to the precise requirements of their designs.
Macrocell Architecture
Each I/O macrocell, as shown in Figure 2, consists of a D-type
flip-flop and two signal-select multiplexers. The configuration of each
macrocell of the P3Z22V10 is determined by the two EEPROM bits
controlling these multiplexers. These bits determine output polarity,
and output type (registered or non-registered). Equivalent circuits for
the macrocell configurations are illustrated in Figure 3.
Output type
The signal from the OR array can be fed directly to the output pin
(combinatorial function) or latched in the D-type flip-flop (registered
function). The D-type flip-flop latches data on the rising edge of the
clock and is controlled by the global preset and clear terms. When
the synchronous preset term is satisfied, the Q output of the register
will be set HIGH at the next rising edge of the clock input. Satisfying
the asynchronous clear term will set Q LOW, regardless of the clock
state. If both terms are satisfied simultaneously, the clear will
override the preset.
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