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參數資料
| 型號： | P28F002BC-T80 |
| 廠商： | INTEL CORP |
| 元件分類： | PROM |
| 英文描述： | 28F002BC 2-MBIT (256K X 8) BOOT BLOCK FLASH MEMORY |
| 中文描述： | 256K X 8 FLASH 12V PROM, 80 ns, PDIP40 |
| 封裝： | PLASTIC, DIP-40 |
| 文件頁數： | 21/37頁 |
| 文件大?。?/td> | 455K |
| 代理商： | P28F002BC-T80 |
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E
28F002BC 2-MBIT BOOT BLOCK FLASH MEMORY
21
PRELIMINARY
SR.7 =
0
1
Start
Write 20H and
Block Address
Write D0H and
Block Address
Full Status
Check if Desired
Block Erase
Complete
FULL STATUS CHECK PROCEDURE
1
0
Read Status Register
Data (See Above)
1
0
Read Status Register
V Range Error
Suspend
Erase
Suspend Erase
Loop
Yes
No
1
0
Command Sequence
Error
SR.3 =
SR.5 =
SR.4,5 =
Block Erase
Error
Bus
Operation
Command
Comments
Standby
Check SR.4,5
Both 1 = Command
Sequence Error
Standby
SR.3 MUST be cleared, if set during an erase attempt, before further
attempts are allowed by the Write State Machine.
SR.5 is only cleared by the Clear Status Register command, in
cases where multiple blocks are erase before full status is checked.
If error is detected, clear the status register before attempting
retry or other error recovery.
Check SR.5
1 = Block Erase Error
Standby
Bus
Operation
Command
Comments
Write
Write
Erase Setup
Read
Data = 20H
Addr = Within Block to Be Erased
Check SR.7
1 = WSM Ready
0 = WSM Busy
Repeat for subsequent block erasures.
Full Status Check can be done after each block erase, or after a
sequence of block erasures.
Write FFH after the last operation to reset device to read array mode.
Status Register Data
Toggle CE# or OE# to Update
Status Register
Standby
Erase
Confirm
Data = D0H
Addr = Within Block to Be Erased
Block Erase
Successful
Check SR.3
1 = V Low Detect
0578_07
Figure 8. Automated Block Erase Flowchart
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相關代理商/技術參數 |
參數描述 |
|---|---|
| P28F010120 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| P28F010-120 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:28F010 1024K (128K X 8) CMOS FLASH MEMORY |
| P28F010150 | 制造商:INTEL 功能描述:* |
| P28F010-150 | 制造商:Intel 功能描述: |
| P28F010-200 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 Flash EEPROM |
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