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參數(shù)資料
| 型號： | P28F002BC-T80 |
| 廠商： | INTEL CORP |
| 元件分類： | PROM |
| 英文描述： | 28F002BC 2-MBIT (256K X 8) BOOT BLOCK FLASH MEMORY |
| 中文描述： | 256K X 8 FLASH 12V PROM, 80 ns, PDIP40 |
| 封裝： | PLASTIC, DIP-40 |
| 文件頁數(shù)： | 19/37頁 |
| 文件大?。?/td> | 455K |
| 代理商： | P28F002BC-T80 |
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E
When the status register indicates that erasure is
complete, the status bits, which indicate whether
the erase operation was successful, should be
checked. If the erase operation was unsuccessful,
bit 5 of the status register will be set (within 1.5 ms)
to
“1,” indicating an erase failure. If V
PP
is not within
acceptable during the suspended period, the WSM
does not execute the erase sequence; instead, bit 5
of the status register is set to a “1” to indicate an
Erase Failure, and bit 3 is set to a “1” to indicate
that the V
PP
supply voltage was outside acceptable
limits.
28F002BC 2-MBIT BOOT BLOCK FLASH MEMORY
19
PRELIMINARY
The status register should be cleared before
attempting the next operation. Any CUI instruction
can follow after erasure is completed; however,
reads
from
the
memory
accomplished until the CUI is given the Read Array
command. Figure 8 details the Automated Block
Erase Flowchart.
array
cannot
be
3.3.4.1
Suspending and Resuming Erase
Since an erase operation may take a few seconds
to complete, an Erase Suspend command is
provided. This allows erase-sequence interruption
in order to read data from another block of the
memory array. Once the erase sequence is started,
writing the Erase Suspend command to the CUI
requests that the WSM pause the erase sequence
at a predetermined point in the erase algorithm. The
status register must then be read to determine if the
erase operation has been suspended. Taking V
PP
below V
PPLK
latches the V
PP
low status and aborts
the operation in progress. V
PP
should be main-
tained at valid levels, even during Erase Suspend.
At this point, a Read Array command can be written
to the CUI in order to read data from blocks other
than that being erased. The only other valid
commands at this time are Erase Resume and
Read Status Register.
During erase suspend mode, the chip can go into a
pseudo-standby mode by taking CE# to V
IH
, which
reduces active current draw.
To resume the erase operation, the chip must be
enabled by taking CE# to V
IL
, then issuing the
Erase Resume command. When the Erase Resume
command is given, the WSM will continue with the
erase sequence and finish erasing the block. As
with the end of a standard erase operation, the
status register must be read, cleared, and the next
instruction issued in order to continue. Figure 9
highlights the Erase Suspend/Resume Flowchart.
3.3.5
EXTENDED CYCLING
Intel has designed extended cycling capability into
its ETOX IV flash memory technology. The
28F002BC flash memory is designed for 100,000
program/erase cycles on each of the five blocks. At
10% V
PP
, the parameter blocks are capable of
10,000 program/erase cycles. The combination of
low electric fields, clean oxide processing and
minimized oxide area per memory cell subjected to
the tunneling electric field results in very high
cycling capability.
3.4
Boot Block Locking
The Boot Block memory architecture features a
hardware-lockable boot block so that the kernel
code for the system can be kept secure while the
parameter and main blocks are programmed and
erased independently as necessary. Only the boot
block can be locked independently from the other
blocks.
3.4.1
V
= V
FOR COMPLETE
PROTECTION
For complete write protection of all blocks in the
flash device, the V
PP
programming voltage can be
held low. When V
PP
is below V
PPLK
, any program or
erase operation will cause the device to set an error
bit in the status register.
3.4.2
RP# = V
FOR BOOT BLOCK
UNLOCKING
In the case of boot block modifications (write and
erase), RP# and V
PP
are set to V
HH
(12V).
However, if RP# is not at V
HH
when a program or
erase operation of the boot block is attempted, the
corresponding status register bit (Bit 4 for Program
and Bit 5 for Erase, refer to Table 5 for status
register definitions) is set to indicate the failure to
complete the specified operation.
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