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參數(shù)資料
| 型號(hào)： | P28F002BC-T120 |
| 廠商： | INTEL CORP |
| 元件分類： | PROM |
| 英文描述： | 28F002BC 2-MBIT (256K X 8) BOOT BLOCK FLASH MEMORY |
| 中文描述： | 256K X 8 FLASH 12V PROM, 120 ns, PDIP40 |
| 封裝： | PLASTIC, DIP-40 |
| 文件頁數(shù)： | 31/37頁 |
| 文件大小： | 455K |
| 代理商： | P28F002BC-T120 |
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E
28F002BC 2-MBIT BOOT BLOCK FLASH MEMORY
31
PRELIMINARY
Table 9. AC Characteristics: WE#
—Controlled Write Operations
(1)
(Continued)
28F002BC-80
28F002BC-120
Symbol
Parameter
Notes
V
CC
= 5V ± 10%
100 pF
V
CC
= 5V ± 10%
100 pF
Units
Min
Max
Min
Max
t
WHWL
WE# Pulse Width High
20
20
ns
t
WHQV1
Duration of Programming Operation
2, 5
6
6
μs
t
WHQV2
Duration of Erase Operation (Boot)
2, 5, 6
0.3
0.3
s
t
WHQV3
Duration of Erase Operation
(Parameter)
2,5
0.3
0.3
s
t
WHQV4
Duration of Erase Operation (Main)
2, 5
0.6
0.6
s
t
QVVL
V
PP
Hold from Valid SRD
RP# V
HH
Hold from Valid SRD
5, 8
0
0
ns
t
QVPH
6, 8
0
0
ns
t
PHBR
Boot Block Lock Delay
7, 8
100
100
ns
NOTES:
1. Read timing characteristics during write and erase operations are the same as during read-only operations. Refer to AC
characteristics during read mode.
2. The on-chip WSM completely automates program/erase operations; program/erase algorithms are now controlled internally
which includes verify and margining operations.
3. Refer to command definition table for valid A
IN
.
4. Refer to command definition table for valid D
IN
.
5. Program/erase durations are measured to valid SRD data (successful operation, SR.7 = 1).
6. For boot block program/erase, RP# should be held at V
HH
until operation completes successfully.
7. Time t
PHBR
is required for successful relocking of the boot block.
8. Sampled, but not 100% tested.
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