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| 型號： | ORSO42G5-3BMN484C |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 19/153頁 |
| 文件大小： | 0K |
| 描述： | IC TRANCEIVERS FPSC 680FPGAM |
| 產(chǎn)品變化通告： | Product Discontinuation 01/Aug/2011 |
| 標準包裝： | 60 |
| 系列： | * |
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Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
115
MPI_ACK
O
In
MPI mode this is driven low indicating the MPI received the data on the write cycle or
returned data on a read cycle.
I/O If not used for MPI these pins are user-programmable I/O pins after conguration.
1
MPI_CLK
I
This is the PowerPC synchronous, positive-edge bus clock used for the
MPI interface. It can be
a source of the clock for the Embedded System Bus. If MPI is used this will be the AMBA bus
clock.
I/O If not used for MPI these pins are user-programmable I/O pins after conguration.
1
MPI_TEA
O
A low on the MPI transfer error acknowledge indicates that the MPI detects a bus error on the
internal system bus for the current transaction.
I/O If not used for MPI these pins are user-programmable I/O pins after conguration.
1
MPI_RTRY
O
This pin requests the MPC860 to relinquish the bus and retry the cycle.
I/O If not used for MPI these pins are user-programmable I/O pins after conguration.
1
D[0:31]
I/O Selectable data bu
s width from 8, 16, 32-bit in MPI mode. Driven by the bus master in a write
transaction and driven by MPI in a read transaction.
I
D[7:0] receive conguration data during master parallel, peripheral, and slave parallel congu-
ration modes when WR is low and each pin has a pull-up enabled. During serial conguration
modes, D0 is the DIN input.
O
D[7:3] output internal status for asynchronous peripheral mode when RD is low.
I/O After conguration, if MPI is not used, the pins are user-programmable I/O pins.
1
DP[0:3]
I/O Selectable parity bus width in MPI mode from 1, 2, 4-bit, DP[0] for D[0:7], DP[1] for D[8:15],
DP[2] for D[16:23], and DP[3] for D[24:31].
After conguration, if MPI is not used, the pins are user-programmable I/O pin.
1
DIN
I
During slave serial or master serial conguration modes, DIN accepts serial conguration data
synchronous with CCLK. During parallel conguration modes, DIN is the D0 input. During con-
guration, a pull-up is enabled.
I/O After conguration, this pin is a user-programmable I/O pin.
1
DOUT
O
During conguration, DOUT is the serial data output that can drive the DIN of daisy-chained
slave devices. Data out on DOUT changes on the rising edge of CCLK.
I/O After conguration, DOUT is a user-programmable I/O pin.
1
TESTCFG
(ORSO82G5 only)
I
During conguration this pin should be held high, to allow conguration to occur. A pull up is
enabled during conguration.
I/O After conguration, TESTCFG is a user programmable I/O pin.
1
1. The FPGA States of Operation section in the ORCA Series 4 FPGAs data sheet contains more information on how to control these signals
during start-up. The timing of DONE release is controlled by one set of bit stream options, and the timing of the simultaneous release of all
other conguration pins (and the activation of all user I/Os) is controlled by a second set of options.
Table 47. Pin Descriptions (Continued)
Symbol
I/O
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ORT82G5-1FN680I | IC TRANCEIVERS FPSC 680FPBGA |
| ORT82G5-2FN680I | IC TRANCEIVERS FPSC 680FPBGA |
| VI-J4H-IW-F4 | CONVERTER MOD DC/DC 52V 100W |
| VI-J4H-IW-F3 | CONVERTER MOD DC/DC 52V 100W |
| ORT82G5-1FN680C | IC TRANCEIVERS FPSC 680FPBGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ORSO42G5-EV | 功能描述:可編程邏輯 IC 開發(fā)工具 Eval Brd ORSO42G5 RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評估:5CEFA7F3 接口類型: 工作電源電壓: |
| ORSO82G5 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:0.6 to 2.7 Gbps SONET Backplane Interface FPSCs |
| ORSO82G5-1BM680C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORSO82G5-1BM680I | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORSO82G5-1F680C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 2.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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