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參數(shù)資料
| 型號： | ORSO42G5-2BMN484C |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 98/153頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TRANCEIVERS FPSC 680FPGAM |
| 產(chǎn)品變化通告： | Product Discontinuation 01/Aug/2011 |
| 標準包裝： | 60 |
| 系列： | * |
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Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
49
Cell Mode Detailed Description
A common application for the ORSO42G5 and ORSO82G5 is to provide a bridge between a port card and a cell-
based switch fabric. In cell mode, the data in the Synchronous Payload Envelope (SPE) of the SONET frames is
further formatted into xed-length cells by the ORSO42G5 and ORSO82G5. The cell contents will typically be
unique to specic port card and switch devices. The ORSO42G5 and ORSO82G5 supports this application with a
“cell mode” of operation
The basic data ows in cell mode are shown in Figure 35. Data to be transmitted is received from the FPGA logic
(see Table 11 and Table 12 for details of the core/FPGA signal assignments in the transmit direction which differ
signicantly from the SERDES only and SONET modes), inserted into the SPE of the SONET frame, scrambled
and transmitted from the SERDES block. In cell mode, multiple SERDES links are used to achieve desired band-
width. A two-link mode is supported in the ORSO42G5 and both two-link and eight-link cell modes are supported.
For such interfaces, data are cell-striped in a round-robin fashion across multiple links by the transmitter.
Figure 35. Basic Data Flows - Cell Mode
In the receive direction, the framed data are received from the SERDES block, descrambled and are passed into a
cell extractor which extracts individual cells from the payload portion of the SONET frame. The cells are then
passed through a FIFO that performs lane-to-lane deskew and a clock domain transfer. The clock domain transfer
is handled automatically using idle cell insertion and deletion.
The cells are passed into either the eight-link Input Port Controller IPC8 block (ORSO82G5 only) or to one of the
two-link IPC2 block(s), which reassemble the cells back into a single cell stream (destriping) which is sent to the
FPGA logic. (See Table 13 and Table 14 for details of the core/FPGA signal assignments in the receive direction.
As with the transmit path, the cell mode assignments differ signicantly from those for the SERDES only and
SONET modes).
SERDES and SONET processing has been described in previous sections and only features unique to the cell
mode will be discussed in the following sections. The cell format will be discussed rst, followed by a description of
the transmit path, which will include either a two-link or an eight-link Output Port Controller (OPC) block, and a
description of the receive path, including the two-link or eight-link Input Port Controller (IPC) blocks.
Cell Formats
Cells are arranged within a SONET (STS-48c) frame as shown in Figure 36. A SONET STS-48c frame has 4176
(87 x 48) columns of SPE and 9 rows that gives a total of 37,584 bytes. In this implementation, data in a SPE is lim-
ited to xed size cells. Though four cell sizes are supported, only one cell size can be used at a time.
User
I/O
Receive (RX) Path
Transmit (TX) Path
Configurable
as
four
or
eight
data
channels
organized
in
two
blocks
MUX/DEMUX
&
SERDES
ORCA 4E04
FPGA Logic
Configurable
Cell
Processing
Pseudo-
SONET
Processing
MUX/DEMUX
and
SERDES
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ORSO42G5-3BMN484C | IC TRANCEIVERS FPSC 680FPGAM |
| ORT82G5-1FN680I | IC TRANCEIVERS FPSC 680FPBGA |
| ORT82G5-2FN680I | IC TRANCEIVERS FPSC 680FPBGA |
| VI-J4H-IW-F4 | CONVERTER MOD DC/DC 52V 100W |
| VI-J4H-IW-F3 | CONVERTER MOD DC/DC 52V 100W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ORSO42G5-2BMN484I | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORSO42G5-3BM484C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORSO42G5-3BMN484C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORSO42G5-EV | 功能描述:可編程邏輯 IC 開發(fā)工具 Eval Brd ORSO42G5 RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評估:5CEFA7F3 接口類型: 工作電源電壓: |
| ORSO82G5 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:0.6 to 2.7 Gbps SONET Backplane Interface FPSCs |
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