參數(shù)資料
型號： ORSO42G5-2BMN484C
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 13/153頁
文件大?。?/td> 0K
描述： IC TRANCEIVERS FPSC 680FPGAM
產(chǎn)品變化通告： Product Discontinuation 01/Aug/2011
標準包裝： 60
系列： *
Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
11
Figure 1. ORSO42G5 and ORSO82G5 Basic Chip Conguration
The ORSO42G5 and ORSO82G5 support aggregate bandwidths over 10Gbps and are targeted towards users
needing high-speed backplane interfaces for SONET and other non-SONET proprietary backplanes. For non-
SONET applications, all SONET functionality is hidden from the user and no prior networking knowledge is
required.
Built using Series 4 recongurable System-on-a-Chip (SoC) architecture, the ORSO42G5 and ORSO82G5 contain
the FPGA base array and an embedded core supporting eight serial data channels, with clock and data recovery
functions, and provides SONET framing, scrambling/descrambling and cell processing on a single monolithic chip
to enable high-speed asynchronous serial data transfer between system devices. Devices can be on the same PC-
board, on separate boards connected across a backplane or connected by cables. The ORSO42G5 and
ORSO82G5 are completely pin-compatible with the ORT42G5 and ORT82G5 devices.
The ORSO42G5 and ORSO82G5 are considered pseudo-SONET devices because they do not support full over-
head processing, pointer processing or meet all SONET jitter/timing requirements. The ORSO42G5 and
ORSO82G5 are designed primarily for use as SONET backplane devices and not for network termination.
Although they format and process data as SONET frames, they cannot terminate data directly on a SONET ring
without additional functionality being implemented in the FPGA logic because the embedded core is not fully
SONET compliant on a stand-alone basis.
The ORSO42G5 and ORSO82G5 embedded cores support the following:
Section/Line Overhead: A1/A2 (framing bytes), B1 (BIP-8), K2 (APS)
Alarms: OOF (Out Of Frame), B1 error, RDI
Two modes of automatic Transport OverHead (TOH) generation and insertion
AIS-L insertion
SPE signal generation which support +/- stuff events (but no pointer processing)
Embedded Core Overview
The functions in the embedded core portion of the ORSO42G5 and ORSO82G5 devices include:
Eight channel 2.7 Gbps serializer/deserializer functions with Clock and Data Recovery (CDR).
Eight-bit Interface to the Series 4 system bus for control and status information exchange.
Embedded
Serial
I/O
Core
(4 or 8 Serial
Channels)
ORCA 4E04-Based
Programmable Logic
FPGA
I/O
相關PDF資料
PDF描述
ORSO42G5-3BMN484C IC TRANCEIVERS FPSC 680FPGAM
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相關代理商/技術參數(shù)
參數(shù)描述
ORSO42G5-2BMN484I 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO42G5-3BM484C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO42G5-3BMN484C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO42G5-EV 功能描述:可編程邏輯 IC 開發(fā)工具 Eval Brd ORSO42G5 RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評估:5CEFA7F3 接口類型: 工作電源電壓:
ORSO82G5 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:0.6 to 2.7 Gbps SONET Backplane Interface FPSCs
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