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| 型號(hào)： | OR2C06A3T100I-DB |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類(lèi)： | FPGA |
| 英文描述： | FPGA, 144 CLBS, 6900 GATES, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁(yè)數(shù)： | 156/196頁(yè) |
| 文件大?。?/td> | 1393K |
| 代理商： | OR2C06A3T100I-DB |
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62
Lattice Semiconductor
Data Sheet
ORCA Series 2 FPGAs
November 2006
ORCA Timing Characteristics
To dene speed grades, the
ORCA Series part number
designation (see Table 54) uses a single-digit number
to designate a speed grade. This number is not related
to any single ac parameter. Higher numbers indicate a
faster set of timing parameters. The actual speed sort-
ing is based on testing the delay in a path consisting of
an input buffer, combinatorial delay through all PLCs in
a row, and an output buffer. Other tests are then done
to verify other delay parameters, such as routing
delays, setup times to FFs, etc.
The most accurate timing characteristics are reported
by the timing analyzer in the ispLEVER development
system. A timing report provided by the development
system after layout divides path delays into logic and
routing delays. The timing analyzer can also provide
logic delays prior to layout. While this allows routing
budget estimates, there is wide variance in routing
delays associated with different layouts.
The logic timing parameters noted in the Electrical
Characteristics section of this data sheet are the same
as those in the design tools. In the PFU timing given in
Tables 31—79, symbol names are generally a concate-
nation of the PFU operating mode (as dened in
Table 5) and the parameter type. The wildcard charac-
ter (*) is used in symbol names to indicate that the
parameter applies to any sub-LUT. The setup, hold,
and propagation delay parameters, dened below, are
designated in the symbol name by the SET, HLD, and
DEL characters, respectively.
The values given for the parameters are the same as
those used during production testing and speed bin-
ning of the devices. The junction temperature and sup-
ply voltage used to characterize the devices are listed
in the delay tables. Actual delays at nominal tempera-
ture and voltage for best-case processes can be much
better than the values given.
It should be noted that the junction temperature used in
the tables is generally 85 °C. The junction temperature
for the FPGA depends on the power dissipated by the
device, the package thermal characteristics (
ΘJA), and
the ambient temperature, as calculated in the following
equation and as discussed further in the Package
Thermal Characteristics section:
TJmax = TAmax + (P
ΘJA) °C
Note: The user must determine this junction tempera-
ture to see if the delays from ispLEVER should
be derated based on the following derating
tables.
Table 14A and 14B and provide approximate power
supply and junction temperature derating for OR2CxxA
commercial and industrial devices. Table 15A and 15B
provides the same information for the OR2TxxA and
OR2TxxB devices (both commercial and industrial).
The delay values in this data sheet and reported by
ispLEVER are shown as 1.00 in the tables. The method
for determining the maximum junction temperature is
dened in the Thermal Characteristics section. Taken
cumulatively, the range of parameter values for best-
case vs. worst-case processing, supply voltage, and
junction temperature can approach 3 to 1.
Table 14A. Derating for Commercial Devices
(OR2CxxA)
Table 14B. Derating for Industrial Devices
(OR2CxxA)
Table 15A. Derating for Commercial/Industrial
Devices (OR2TxxA)
TJ
(°C)
Power Supply Voltage
4.75 V
5.0 V
5.25 V
0
0.81
0.79
0.77
25
0.85
0.83
0.81
85
1.00
0.97
0.95
100
1.05
1.02
1.00
125
1.12
1.09
1.07
TJ
(°C)
Power Supply Voltage
4.5 V
4.75 V
5.0 V
5.25 V
5.5 V
–40
0.71
0.70
0.68
0.66
0.65
0
0.80
0.78
0.76
0.74
0.73
25
0.84
0.82
0.80
0.78
0.77
85
1.00
0.97
0.94
0.93
0.91
100
1.05
1.01
0.99
0.97
0.95
125
1.12
1.09
1.06
1.04
1.02
TJ
(°C)
Power Supply Voltage
3.0 V
3.3 V
3.6 V
–40
0.73
0.66
0.61
0
0.82
0.73
0.68
25
0.87
0.78
0.72
85
1.00
0.90
0.83
100
1.04
0.94
0.87
125
1.10
1.00
0.92
Select
devices
have
been
discontinued.
See
Ordering
Information
section
for
product
status.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| OR2C06A3T144I-DB | FPGA, 144 CLBS, 6900 GATES, PQFP144 |
| OR2C06A4T100-DB | FPGA, 144 CLBS, 6900 GATES, PQFP100 |
| OR2C15A-2B256 | FPGA, 400 CLBS, 15000 GATES, PBGA256 |
| OR2C15A-3B256 | FPGA, 400 CLBS, 15000 GATES, PBGA256 |
| OR2C15A-4B256 | FPGA, 400 CLBS, 15000 GATES, PBGA256 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OR2C06A-3T144 | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Field-Programmable Gate Arrays |
| OR2C06A-3T144I | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Field-Programmable Gate Arrays |
| OR2C06A3T144I-DB | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 Use ECP/EC or XP RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR2C06A-3T160 | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Field-Programmable Gate Arrays |
| OR2C06A-3T160I | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Field-Programmable Gate Arrays |
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