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| 型號： | OR2C06A3T100I-DB |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 144 CLBS, 6900 GATES, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數(shù)： | 148/196頁 |
| 文件大小： | 1393K |
| 代理商： | OR2C06A3T100I-DB |
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Lattice Semiconductor
55
Data Sheet
November 2006
ORCA Series 2 FPGAs
Special Function Blocks (continued)
Global 3-State Control (TS_ALL)
The TS_ALL block resides in the upper-right corner of
the FPGA array.
To increase the testability of the
ORCA Series FPGAs,
the global 3-state function (TS_ALL) disables the
device. The TS_ALL signal is driven from either an
external pin or an internal signal. Before and during
conguration, the TS_ALL signal is driven by the input
pad RD_CFG. After conguration, the TS_ALL signal
can be disabled, driven from the RD_CFG input pad, or
driven by a general routing signal in the upper-right cor-
ner. Before conguration, TS_ALL is active-low; after
conguration, the sense of TS_ALL can be inverted.
The following occur when TS_ALL is activated:
1. All of the user I/O output buffers are 3-stated, the
user I/O input buffers are pulled up (with the pull-
down disabled), and the input buffers are congured
with TTL input thresholds (OR2CxxA only).
2. The TDO/RD_DATA output buffer is 3-stated.
3. The RD_CFG, RESET, and PRGM input buffers remain
active with a pull-up.
4. The DONE output buffer is 3-stated, and the input
buffer is pulled-up.
Internal Oscillator
The internal oscillator resides in the lower-left corner of
the FPGA array. It has output clock frequencies of
1.25 MHz and 10 MHz. The internal oscillator is the
source of the internal CCLK used for conguration. It
may also be used after conguration as a general-
purpose clock signal.
Global Set/Reset (GSRN)
The GSRN logic resides in the lower-right corner of the
FPGA. GSRN is an invertible, default, active-low signal
that is used to reset all of the user-accessible latches/
FFs on the device. GSRN is automatically asserted at
powerup and during conguration of the device.
The timing of the release of GSRN at the end of cong-
uration can be programmed in the start-up logic
described below. Following conguration, GSRN may
be connected to the RESET pin via dedicated routing,
or it may be connected to any signal via normal routing.
Within each PFU, individual FFs and latches can be
programmed to either be set or reset when GSRN is
asserted.
The RESET input pad has a special relationship to
GSRN. During conguration, the RESET input pad
always initiates a conguration abort, as described in
the FPGA States of Operation section. After congura-
tion, the global set/reset signal (GSRN) can either be
disabled (the default), directly connected to the RESET
input pad, or sourced by a lower-right corner signal. If
the RESET input pad is not used as a global reset after
conguration, this pad can be used as a normal input
pad.
Start-Up Logic
The start-up logic block is located in the lower right cor-
ner of the FPGA. This block can be congured to coor-
dinate the relative timing of the release of GSRN, the
activation of all user I/Os, and the assertion of the
DONE signal at the end of conguration. If a start-up
clock is used to time these events, the start-up clock
can come from CCLK, or it can be routed into the start-
up block using lower-right corner routing resources.
These signals are described in the Start-Up subsection
of the FPGA States of Operation section.
Select
devices
have
been
discontinued.
See
Ordering
Information
section
for
product
status.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| OR2C06A3T144I-DB | FPGA, 144 CLBS, 6900 GATES, PQFP144 |
| OR2C06A4T100-DB | FPGA, 144 CLBS, 6900 GATES, PQFP100 |
| OR2C15A-2B256 | FPGA, 400 CLBS, 15000 GATES, PBGA256 |
| OR2C15A-3B256 | FPGA, 400 CLBS, 15000 GATES, PBGA256 |
| OR2C15A-4B256 | FPGA, 400 CLBS, 15000 GATES, PBGA256 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OR2C06A-3T144 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Gate Arrays |
| OR2C06A-3T144I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Gate Arrays |
| OR2C06A3T144I-DB | 功能描述:FPGA - 現(xiàn)場可編程門陣列 Use ECP/EC or XP RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR2C06A-3T160 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Gate Arrays |
| OR2C06A-3T160I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Gate Arrays |
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