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參數(shù)資料
| 型號(hào)： | OPA651P |
| 英文描述： | IC-LOW POWER OP-AMP |
| 中文描述： | 集成電路低功耗運(yùn)算腺苷 |
| 文件頁(yè)數(shù)： | 9/12頁(yè) |
| 文件大小： | 114K |
| 代理商： | OPA651P |
9
OPA651
Operating junction temperature (T
J
) is given by T
A
+
P
D
θ
JA
. The total internal power dissipation (P
D
) is a com-
bination of the total quiescent power (P
DQ
) and the power
dissipated in of the output stage (P
DL
) to deliver load
power. Quiescent power is simply the specified no-load
supply current times the total supply voltage across the
part. P
DL
will depend on the required output signal and load
but would, for a grounded resistive load, be at a maximum
when the output is a fixed DC voltage equal to 1/2 of either
supply voltage (assuming equal bipolar supplies). Under
this condition, P
DL
= V
S2
/(4R
L
) where R
L
includes feed-
back network loading. Note that it is the power dissipated
in the output stage and not in the load that determines
internal power dissipation. As an example, compute the
maximum T
J
for an OPA651N at A
V
= +2, R
L
= 100
, R
FB
= 402
,
±
V
S
=
±
5V, with the output at |V
S
/2|, and the
specified maximum T
A
= +85
°
C. P
D
= 10V8.75mA + (5
2
)/
(4(100
||804
)) = 158mW. Maximum T
J
= +85
°
C +
0.158W150
°
C/W = 109
°
C.
DRIVING CAPACITIVE LOADS
The OPA651’s output stage has been optimized to drive low
resistive loads. Capacitive loads, however, will decrease the
amplifier’s phase margin which may cause high frequency
peaking or oscillations. Capacitive loads greater than 10pF
should be isolated by connecting a small resistance, usually
15
to 30
, in series with the output as shown in Figure 4.
This is particularly important when driving high capacitance
loads such as flash A/D converters. Increasing the gain from
+2 will improve the capacitive load drive due to increased
phase margin.
In general, capacitive loads should be minimized for opti-
mum high frequency performance. Coax lines can be driven
if the cable is properly terminated. The capacitance of coax
cable (29pF/foot for RG-58) will not load the amplifier
when the coaxial cable or transmission line is terminated in
its characteristic impedance.
that, from a stability standpoint, an inverting gain of –1V/V
is equivalent to a noise gain of 2.) Frequency response for
other gains are shown in the Typical Performance Curves.
The high frequency response of the OPA651 in a good
layout is very flat with frequency. However, some circuit
configurations such as those where large feedback resis-
tances are used, can produce high-frequency gain peaking.
This peaking can be minimized by connecting a small
capacitor in parallel with the feedback resistor. This capaci-
tor compensates for the closed-loop, high-frequency, trans-
fer function zero that results from the time constant formed
by the input capacitance of the amplifier (typically 2pF after
PC board mounting), and the input and feedback resistors.
The selected compensation capacitor may be a trimmer, a
fixed capacitor, or a planned PC board capacitance. The
capacitance value is strongly dependent on circuit layout and
closed-loop gain. Using small resistor values will preserve
the phase margin and avoid peaking by keeping the break
frequency of this zero sufficiently high. When high closed-
loop gains are required, a three-resistor attenuator (tee-
network) is recommended to avoid using large value resis-
tors with large time constants. The OPA651 includes an
internal 1.5pF feedback capacitor to achieve best gain of +2
flatness (R
F
= 402
).
PULSE SETTLING TIME
High speed amplifiers like the OPA651 are capable of
extremely fast settling time with a pulse input. Excellent
frequency response flatness and phase linearity are required
to get the best settling times. As shown in the specifications
table, settling time for a
±
1V step at a gain of +2 for the
OPA651 is extremely fast. The specification is defined as
the time required, after the input transition, for the output to
settle within a specified error band around its final value. For
a 2V step, 1% settling corresponds to an error band of
±
20mV, 0.1% to an error band of
±
2mV, and 0.01% to an
error band of
±
0.2mV. For the best settling times, particu-
larly into an ADC capacitive load, little or no peaking in the
frequency response can be allowed. Using the recommended
R
ISO
for capacitive loads will limit this peaking and reduce
the settling times. Fast, extremely fine scale settling (0.01%)
requires close attention to ground return currents in the
supply decoupling capacitors. For highest performance, con-
sider the OPA642 which isolates the output stage decoupling
from the rest of the amplifier.
DIFFERENTIAL GAIN AND PHASE
Differential Gain (DG) and Differential Phase (DP) are
among the more important specifications for video applica-
tions. The percentage change in closed-loop gain over a
specified change in output voltage level is defined as DG.
DP is defined as the change in degrees of the closed-loop
phase over the same output voltage change. DG and DP are
both specified at the NTSC sub-carrier frequency of 3.58MHz.
All measurements were performed using an HP 9480.
FIGURE 4. Driving Capacitive Loads.
OPA651
C
L
R
L
R
ISO
(R
ISO
typically 15
to 30
)
402
402
FREQUENCY RESPONSE COMPENSATION
The OPA651 is internally compensated and is stable at a
gain of 2 with a phase margin of approximately 60
°
. (Note
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PDF描述 |
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| OPA658N-250 | Current-Feedback Operational Amplifier |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OPA651U | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| OPA651U/2K5 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| OPA651UB | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| OPA65250 | 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:Wideband, Unity-Gain Stable, FET-Input OPERATIONAL AMPLIFIER |
| OPA652K5 | 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:Wideband, Unity-Gain Stable, FET-Input OPERATIONAL AMPLIFIER |
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