參數(shù)資料
型號(hào)： OPA2634
英文描述： Dual, Wideband, Single-Supply OPERATIONAL AMPLIFIER
中文描述： 雙路，寬帶，單電源運(yùn)算放大器
文件頁(yè)數(shù)： 14/16頁(yè)
文件大?。?/td> 155K
代理商： OPA2634
14
OPA2634
The Typical Performance Curves show the recommended
R
S
versus capacitive load and the resulting frequency re-
sponse at the load. Parasitic capacitive loads greater than
2pF can begin to degrade the performance of the OPA2634.
Long PC board traces, unmatched cables, and connections to
multiple devices can easily exceed this value. Always con-
sider this effect carefully, and add the recommended series
resistor as close as possible to the output pin (see Board
Layout Guidelines).
The criterion for setting this R
S
resistor is a maximum
bandwidth, flat frequency response at the load. For a gain of
+2, the frequency response at the output pin is already
slightly peaked without the capacitive load, requiring rela-
tively high values of R
S
to flatten the response at the load.
Increasing the noise gain will also reduce the peaking,
reducing the required R
S
value (see Figure 6).
DISTORTION PERFORMANCE
The OPA2634 provides good distortion performance into a
150
load. Relative to alternative solutions, it provides
exceptional performance into lighter loads and/or operating
on a single +3V supply. Generally, until the fundamental
signal reaches very high frequency or power levels, the 2nd
harmonic will dominate the distortion with a negligible 3rd
harmonic component. Focusing then on the 2nd harmonic,
increasing the load impedance improves distortion directly.
Remember that the total load includes the feedback network;
in the non-inverting configuration (Figure 1) this is sum of
R
F
+ R
G
, while in the inverting configuration, it is just R
F
.
NOISE PERFORMANCE
High slew rate, unity gain stable, voltage-feedback op amps
usually achieve their slew rate at the expense of a higher
input noise voltage. The 5.6nV/
√
Hz input voltage noise for
the OPA2634 is, however, much lower than comparable
amplifiers. The input-referred voltage noise, and the two
input-referred current noise terms (2.8pA/
√
Hz), combine to
give low output noise under a wide variety of operating
conditions. Figure 8 shows the op amp noise analysis model
with all the noise terms included. In this model, all noise
terms are taken to be noise voltage or current density terms
in either nV/
√
Hz or pA/
√
Hz.
The total output spot noise voltage can be computed as the
square root of the sum of all squared output noise voltage
contributors. Equation 1 shows the general form for the
output noise voltage using the terms shown in Figure 8.
Equation 1:
Dividing this expression by the noise gain (NG = (1+R
F
/R
G
))
will give the equivalent input-referred spot noise voltage at
the non-inverting input, as shown in Equation 2.
4kT
R
G
R
G
R
F
R
S
1/2
OPA2634
I
BI
E
O
I
BN
4kT = 1.6E –20J
at 290
°
K
E
RS
E
NI
4kTR
S
√
4kTR
F
√
FIGURE 8. Noise Analysis Model.
Equation 2:
Evaluating these two equations for the circuit and compo-
nent values shown in Figure 1 will give a total output spot
noise voltage of 12.5nV/
√
Hz and a total equivalent input
spot noise voltage of 6.3nV/
√
Hz. This is including the noise
added by the resistors. This total input-referred spot noise
voltage is not much higher than the 5.6nV/
√
Hz specification
for the op amp voltage noise alone. This will be the case as
long as the impedances appearing at each op amp input are
limited to the previously recommend maximum value of
400
, and the input attenuation is low.
DC ACCURACY AND OFFSET CONTROL
The balanced input stage of a wideband voltage-feedback op
amp allows good output DC accuracy in a wide variety of
applications. The power supply current trim for the OPA2634
gives even tighter control than comparable products. Al-
though the high-speed input stage does require relatively
high input bias current (typically 25
μ
A out of each input
terminal), the close matching between them may be used to
reduce the output DC error caused by this current. This is
done by matching the DC source resistances appearing at the
two inputs. Evaluating the configuration of Figure 1 (which
has matched DC input resistances), using worst-case +25
°
C
input offset voltage and current specifications, gives a worst-
case output offset voltage equal to (NG = non-inverting
signal gain at DC):
±
(NG V
OS(MAX)
)
±
(R
F
I
OS(MAX)
)
=
±
(1 7.0mV)
±
(750
2.0
μ
A)
=
±
8.5mV = Output Offset Range for Figure 1
E
N
=
E
NI
2
+
I
BN
R
S
(
)
2
+ 4
kTR
S
+
I
BI
R
F
NG
2
+4
kTR
F
NG
E
O
=
E
NI
2
+
I
BN
R
S
(
)
2
+ 4
kTR
S
(
)
NG
2
+
I
BI
R
F
(
)
2
+ 4
kTR
F
NG
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