參數(shù)資料
型號: OPA2634
英文描述: Dual, Wideband, Single-Supply OPERATIONAL AMPLIFIER
中文描述: 雙路,寬帶,單電源運算放大器
文件頁數(shù): 13/16頁
文件大?。?/td> 155K
代理商: OPA2634
13
OPA2634
PC board trace or other transmission line conductor), R
G
may be set equal to the required termination value and R
F
adjusted to give the desired gain. This is the simplest
approach and results in optimum bandwidth and noise per-
formance. However, at low inverting gains, the resultant
feedback resistor value can present a significant load to the
amplifier output. For an inverting gain of 2, setting R
G
to
50
for input matching eliminates the need for R
M
but
requires a 100
feedback resistor. This has the interesting
advantage that the noise gain becomes equal to 2 for a 50
source impedance—the same as the non-inverting circuits
considered above. However, the amplifier output will now
see the 100
feedback resistor in parallel with the external
load. In general, the feedback resistor should be limited to
the 200
to 1.5k
range. In this case, it is preferable to
increase both the R
F
and R
G
values as shown in Figure 7, and
then achieve the input matching impedance with a third
resistor (R
M
) to ground. The total input impedance becomes
the parallel combination of R
G
and R
M
.
The second major consideration, touched on in the previous
paragraph, is that the signal source impedance becomes
part of the noise gain equation and hence, influences the
bandwidth. For the example in Figure 7, the R
M
value
combines in parallel with the external 50
source imped-
ance, yielding an effective driving impedance of 50
||
57.6
= 26.8
. This impedance is added in series with R
G
for calculating the noise gain. The resultant is 2.87 for
Figure 7, as opposed to only 2 if R
M
could be eliminated as
discussed above. The bandwidth will, therefore, be lower
for the gain of –2 circuit of Figure 7 (NG = +2.9) than for
the gain of +2 circuit of Figure 1.
The third important consideration in inverting amplifier
design is setting the bias current cancellation resistors on the
non-inverting input (parallel combination of R
T
= 750
). If
this resistor is set equal to the total DC resistance looking out
of the inverting node, the output DC error, due to the input
bias currents, will be reduced to (Input Offset Current) R
F
.
Because of the 0.1
μ
F capacitor, the inverting input’s bias
current flows through RF. Thus, R
T
= 750
= 1.50k
||
1.50k
is needed for the minimum output offset voltage. To
reduce the additional high frequency noise introduced by R
T
,
and power supply feedthrough, it is bypassed with a 0.1
μ
F
capacitor. At a minimum, the OPA2634 should see a source
resistance of at least 50
to damp out parasitic-induced
peaking—a direct short to ground on the non-inverting input
runs the risk of a very high frequency instability in the input
stage.
OUTPUT CURRENT AND VOLTAGE
The OPA2634 provides outstanding output voltage capabil-
ity. Under no-load conditions at +25
°
C, the output voltage
typically swings closer than 140mV to either supply rail; the
guaranteed swing limit is within 450mV of either rail (V
S
=
+5V).
The minimum specified output voltage and current specifi-
cations over temperature are set by worst-case simulations at
the cold temperature extreme. Only at cold start-up will the
output current and voltage decrease to the numbers shown in
the guaranteed tables. As the output transistors deliver power,
their junction temperatures will increase, decreasing their
V
BE
’s (increasing the available output voltage swing) and
increasing their current gains (increasing the available out-
put current). In steady-state operation, the available output
voltage and current will always be greater than that shown
in the over-temperature specifications since the output stage
junction temperatures will be higher than the minimum
specified operating ambient.
To maintain maximum output stage linearity, no output
short-circuit protection is provided. This will not normally
be a problem since most applications include a series match-
ing resistor at the output that will limit the internal power
dissipation if the output side of this resistor is shorted to
ground.
DRIVING CAPACITIVE LOADS
One of the most demanding and yet very common load
conditions for an op amp is capacitive loading. Often, the
capacitive load is the input of an A/D converter—including
additional external capacitance which may be recommended
to improve A/D linearity. A high-speed, high open-loop gain
amplifier like the OPA2634 can be very susceptible to
decreased stability and closed-loop response peaking when
a capacitive load is placed directly on the output pin. When
the primary considerations are frequency response flatness,
pulse response fidelity and/or distortion, the simplest and
most effective solution is to isolate the capacitive load from
the feedback loop by inserting a series isolation resistor
between the amplifier output and the capacitive load.
FIGURE 7. Gain of –2 Example Circuit.
50
R
F
750
R
G
374
R
M
57.6
Source
+5V
2R
T
1.50k
2R
T
1.50k
R
O
50
0.1
μ
F
6.8
μ
F
+
0.1
μ
F
0.1
μ
F
50
Load
1/2
OPA2634
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