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參數(shù)資料
| 型號： | OM6211U |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 48 X 84 dot matrix LCD driver |
| 中文描述： | 48 × 84點(diǎn)陣LCD驅(qū)動器 |
| 文件頁數(shù)： | 6/48頁 |
| 文件大小： | 243K |
| 代理商： | OM6211U |
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2002 Jan 17
6
Philips Semiconductors
Product specification
48
×
84 dot matrix LCD driver
OM6211
In order to reduce current consumption related to the
pull-up circuitry, the 5-bit number is stored in a register
when exiting the Power-down mode. The pull-up circuitry
is then disabled. Additionally, the register is refreshed by
each HVE command.
7.7
SDIN: serial data input
Serial data input.
7.8
SDOUT: serial data output
Serial data output (3-state, push-pull). If bidirectional data
transmission is required, SDOUT and SDIN should be
connected externally. If the read mode is not used,
SDOUT should be left open-circuit.
7.9
SCLK: serial clock input
Serial clock input.
7.10
SCE: chip enable
Chip enable input, active LOW. If SCE is HIGH, the SCLK
pulses are ignored.
7.11
OSC: oscillator
External clock input. The external clock is active only in a
special test mode, so in the application it is not available.
In normal mode (the internal on-chip oscillator used) this
input must be connected to V
SS
. If OSC is held HIGH, the
internal oscillator is disabled.
7.12
MX: horizontal mirroring
Horizontal mirroring input. When MX = 1 the X address
space is mirrored.
7.13
ID3 and ID4: identification inputs
LCD module identification inputs. Their state can be read
out via the serial interface in order to identify the module
version.
7.14
RES: reset
External reset pin. When LOW the chip will be reset as
defined in Section 9.1. The initialization by the RES pin is
always required during power-on. Timing for the RES pin
is illustrated in Fig.18.
7.15
T1, T2, T3, T4, T5 and T6: test pins
Test pins. In the application T4 and T5 must be connected
toV
SS
.T1, T2, T3 and T6mustbeleftopen-circuit(T6 has
a pull-down resistor).
8
BLOCK DIAGRAM FUNCTIONS
8.1
Oscillator
The on-chip oscillator provides the clock signal for the
display system. It has no external components.
8.2
Serial interface control
Detects the serial interface protocol, commands and
display data bytes. The serial interface converts the data
input (serial-to-parallel) as well as the output bits.
8.3
Command decoder
Decodes all commands.
8.4
Display Data RAM (DDRAM)
The OM6211 contains a 48
×
84 bit static RAM which
stores the display data. The RAM is divided into six banks
of 84 bytes (6
×
8
×
84 bits). During RAM access, data is
transferred to the RAM via the serial interface. There is a
directcorrespondencebetweentheX addressandcolumn
output number.
8.5
Timing generator
The timing generator produces the various signals
required to drive the internal circuitry. Internal chip
operation is not disturbed by operations of the serial
interface.
8.6
Address Counter (AC)
The address counter assigns addresses to the display
data RAM for writing. The X address (X
6
to X
0
) and the
Y address (Y
2
to Y
0
) are set separately. After a write
operation the address counter is automatically
incremented by 1.
8.7
Display address counter
The display is generated by continuously shifting rows of
RAM data to the dot matrix LCD via the column outputs.
The display status (all dots on/off, normal/inverse video) is
set via the serial interface.
8.8
V
LCD
generator
A voltage multiplier (charge pump) with a programmable
number of stages. Internal capacitors are used for the
voltage multiplier, therefore only decoupling capacitors for
V
LCD
and V
DD2
are required.
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