參數(shù)資料
型號(hào): OM6211U
廠商: NXP Semiconductors N.V.
英文描述: 48 X 84 dot matrix LCD driver
中文描述: 48 × 84點(diǎn)陣LCD驅(qū)動(dòng)器
文件頁(yè)數(shù): 30/48頁(yè)
文件大?。?/td> 243K
代理商: OM6211U
2002 Jan 17
30
Philips Semiconductors
Product specification
48
×
84 dot matrix LCD driver
OM6211
All OTP circuitry of the OM6211 is disabled until the
‘Enable OTP’ command is given. Once enabled, the
reading of data from the OTP cells is initiated by either:
Exit from Power-down mode
The ‘Refresh’ command.
It should be noted that in both cases the reading operation
needs up to 5 ms to complete.
The shifting of data into the shift register is performed in a
special mode called CALMM. In the OM6211 the CALMM
mode is entered through the CALMM command. Once in
the CALMM mode the data is shifted into the shift register
via the serial interface at the rate of 1-bit per command.
After transmitting the last (14th) bit and exiting the CALMM
mode the serial interface returns to the normal mode and
allothercommandscanbesent.Careshouldbetakenthat
all 14 bits of data (or a multiple of 14) are transferred
before exiting the CALMM mode, otherwise the bits will be
in the wrong positions.
In the shift register the value of the seal bit is, like the
others, always zero at reset. To ensure that the security
feature works correctly, the CALMM command is disabled
until a refresh has been performed. Once the refresh is
completed, the seal bit value in the shift register is valid
and permission to enter CALMM mode can thus be
determined.
The 14 bits are shifted into the shift register in a predefined
order: firstly the 8 bits of MMOTPVOP
7
to MMOTPVOP
0
,
then the 5 bits of MMVOPCAL
4
to MMVOPCAL
0
and lastly
the seal bit. The MSB is always first, thus the first bit
shifted is MMOTPVOP
7
and the two last bits are
MMVOPCAL
0
and the seal bit.
handbook, full pagewidth
DATA TO THE CIRCUIT FOR
CONFIGURATION AND CALIBRATION
SHIFT
REGISTER
FLIP-FLOP
OTP slice
OTP CELL
SHIFT
REGISTER
SHIFT
REGISTER
DATA
INPUT
read data
from the
OTP cell
write data
to the
OTP cell
OTP CELLs
MGU289
Fig.22 Basic OTP architecture.
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