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| 型號： | OM13013,598 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 18/61頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD DEMO IAR LPC1227 JLINKLITE |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | MCU |
| 適用于相關(guān)產(chǎn)品： | LPC1227 |
| 所含物品： | 板 |
| 其它名稱： | 568-6885 |
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LPC122X
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 26 August 2011
25 of 61
NXP Semiconductors
LPC122x
32-bit ARM Cortex-M0 microcontroller
The system oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be
boosted to a higher frequency, up to the maximum CPU operating frequency, by the
system PLL. The ARM processor clock frequency is referred to as CCLK elsewhere in this
document.
7.18.1.3
Watchdog oscillator
The watchdog oscillator can be used as a clock source that directly drives the CPU, the
watchdog timer, or the CLKOUT pin. The watchdog oscillator nominal frequency is
programmable between 7.8 kHz and 1.7 MHz. The frequency spread over processing and
temperature is
40 %.
7.18.2 System PLL
The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input
frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO).
The multiplier can be an integer value from 1 to 32. The CCO operates in the range of
156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within
its frequency range while the PLL is providing the desired output frequency. The output
divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. The PLL output
frequency must be lower than 100 MHz. Since the minimum output divider value is 2, it is
insured that the PLL output has a 50 % duty cycle. The PLL is turned off and bypassed
following a chip reset and may be enabled by software. The program must configure and
activate the PLL, wait for the PLL to lock, and then connect to the PLL as a clock source.
The PLL settling time is 100
s.
7.18.3 Clock output
The LPC122x features a clock output function that routes the IRC oscillator, the system
oscillator, the watchdog oscillator, or the main clock to an output pin.
7.18.4 Wake-up process
The LPC122x begin operation at power-up and when awakened from Deep power-down
mode by using the 12 MHz IRC oscillator as the clock source. This allows chip operation
to resume quickly. If the main oscillator or the PLL is needed by the application, software
will need to enable these features and wait for them to stabilize before they are used as a
clock source.
7.18.5 Power control
The LPC122x support a variety of power control features. There are three special modes
of processor power reduction: Sleep mode, Deep-sleep mode, and Deep power-down
mode. The CPU clock rate may also be controlled as needed by changing clock sources,
reconfiguring PLL values, and/or altering the CPU clock divider value. This allows a
trade-off of power versus processing speed based on application requirements. In
addition, a register is provided for shutting down the clocks to individual on-chip
peripherals, allowing fine tuning of power consumption by eliminating all dynamic power
use in any peripherals that are not required for the application. Selected peripherals have
their own clock divider which provides even better power control.
7.18.5.1
Sleep mode
When Sleep mode is entered, the clock to the core is stopped. Resumption from the Sleep
mode does not need any special sequence but re-enabling the clock to the ARM core.
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