參數(shù)資料
型號(hào)： NTE6664
廠商： NTE Electronics, Inc.
英文描述： Integrated Circuit 64K-Bit Dynamic RAM
中文描述： 集成電路64K的位動(dòng)態(tài)隨機(jī)存儲(chǔ)器
文件頁數(shù)： 4/5頁
文件大?。?/td> 39K
代理商： NTE6664
Note 8. The transition time specification applies for all input signals. In addition to meeting the transi-
tion rate specification, all input signals must transmit between V
IH
and V
IL
(or between V
IL
and V
IH
) in a monotonic manner.
Note 9. The specification for t
RC
(min) and t
RMW
(min) are used only to indicate cycle time at which
proper operation over the full temperature range (0
°
C
≤
T
A
≤
+70
°
C) is assured.
Note10. AC measurements t
T
= 5ns.
Note11. Assumes that t
RCD
≤
t
RCD
(max).
Note12. Assumes that t
RCD
≥
t
RCD
(max).
Note13. Measured with a current load equivalent to 2 TTL (
–
200
μ
A, +4mA) loads and 100pF with the
data output trip points set at V
OH
= 2V and V
OL
= 0.8V.
Note14. Operation within the t
RCD
(max) limit ensures that t
RAC
(max) can be met, t
RCD
(max) is speci-
fied as a reference point only; if t
RCD
is greater than the specified t
RCD
(max) limit, then ac-
cess time is controlled exclusively by t
CAC
.
Note15. Either t
RRH
or t
RCH
must be satisfied for a read cycle.
Note16. These parameters are referenced to CAS leading edge in random write cycles and to WRITE
leading edge in delayed write or read
–
modify
–
write cycles.
Note17. t
WCS
, t
CWD
, and t
RWD
are not restrictive operating parameters. They are included in the data
sheet as electrical characteristics only; if t
WCS
≥
t
WCS
(min), the cycle is an early write cycle
and the data out pin will remain open circuit (high impedance) throughout the entire cycle;
if t
CWD
≥
t
CWD
(min) and t
RWD
≥
t
RWD
(min), the cycle is read
–
write cycle and the data out will
contain data read from the selected cell; if neither of the above sets of conditions is satisfied,
the condition of the data out (at access time) is indeterminate.
Note19. t
OFF
(max) defines the time at which the output achieves the open circuit condition and is not
referenced to output voltage levels.
A
I
C
C
Precharge
Clock
Memory
Array
Memory
Array
Memory
Array
Memory
Array
Row Decoder
Row Decoder
Precharge
Clock
Memory
Array
Memory
Array
Memory
Array
Memory
Array
Row Decoder
Row Decoder
A0
A1
A2
A3
A4
A5
A6
A7
RAS
CAS
Write, W
REFRESH
Data In, D
Output Data, Q
V
CC
V
SS
Block Diagram
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