參數(shù)資料
型號(hào)： NT68F62
廠商： Electronic Theatre Controls, Inc.
英文描述： 8-Bit Microcontroller for Monitor (32K Flash MTP Type)
中文描述： 8位微控制器的監(jiān)視器（32K閃存中期型）
文件頁數(shù)： 30/57頁
文件大?。?/td> 521K
代理商： NT68F62
NT68F62
30
Self test pattern: On activating the free running function, the system will generate the test pattern when clearing the
ENPAT
bit. The PORT14 pin will switch from I/O pin to pattern output pin (push-pull structure). The system provides four types of test
patterns. Refer to the figure below. Set the
PAT0
bits to select the pattern type (Figure 13.8). If the free run function has not
been enabled, any change of
ENPAT
&
PAT0
bits will be invalid. Refer to the Figure 13.9 for the porch time of the video
pattern.
PAT0
Test Pattern
Note
0
(1)
Only activated when
ENPAT
bit is cleared
1
(2)
The porches of the self test pattern are listed below:
Free Running
Freq.
VBLANK
1
128
μ
s
2
90.5
μ
s
3
51
μ
s
4
51.5
μ
s
5
46.6
μ
s
Front Porch of
BACK Porch of
VBLANK
864
μ
s
589
μ
s
528
μ
s
596
μ
s
515
μ
s
Front Porch of
HBLANK
460ns
BACK Porch of
HBLANK
2.00
μ
s
1.93
μ
s
1.92
μ
s
1.94
μ
s
1.94
μ
s
VSYNC
PULSE WIDTH
64
μ
s
64
μ
s
64
μ
s
64
μ
s
64
μ
s
HSYNC
PULSE WIDTH
1
μ
s
1
μ
s
1
μ
s
1
μ
s
1
μ
s
1.18
μ
s
424ns
185ns
436ns
Mode change detection: The system provides a hardware detection of a Sync signal change and supports the user to
respond to this transition with a proper process as soon as possible. There are three kinds of detection that will set the
INTMUTE bit.
Hsync counter: Users can enable the HDIFF comparison by clearing the
ENHDIFF
bit and then preloading a different value
to the HDIFF0-3 bits in the AUTOMUTE control register ($000E). The system will latch the new value of theHsync counter
and compare it with the last latched value. If this difference is great than the user defined value at theHDIFF0-3 bits then the
system will set the INTMUTE interrupt bit.
H/V polarity: Users can enable polarity detection by clearing the
ENPOL
bit. The system will set the INTMUTE bit when the
polarity of Hsync or Vsync have been changed.
H/V counter overflow: Users can enable the detection of sync counters overflow by clearing the
ENOVER
bit. The system
will set the INTMUTE bit whenever the counter of Hsync or Vsync has overflowed.
The above three sources of setting this INTMUTE bit can be enabled or disabled by user. If the user opens this interrupt and
this interrupt event occured, the system will generate a NMI interrupt to remind users any time. At the user's manipulation, a
software debounce to confirm the transition of a sync signal one more time will make the frequency detection more stable
and reliable, but it will affect the response time. After the system reset, this 'automute' function will be disabled and the
HDIFF0~2 control bits will be cleared to ' $0F'.
HALFHI
HALFHO: Half freq. Output signal (50% duty)
HALFHO output signal when NOHALF bit clear to LOW
(the same signal as in the HALFHI pin)
Figure 13.7. Half Freq. Sync. Waveform
相關(guān)PDF資料
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