
NT6862-5xxxx
36
1
2
3
4
9
1
2
3
4
5
6
7
INTV
8
9
1
2
Vsync Pulse
ENDDC
(in CH0CON register)
INTTX
8
7
6
8
7
6
5
4
3
2
1
Shift
register
SDA
1
8
7
Null
Bit
5
4
3
1
8
6
2
Null
Bit
5
7
MSB
LSB
Second Byte Data
First Byte Data
Invalid data
User can load next byte data
to CH0TXDAT register
Load data in the CH0TXDAT
register to shift register
Figure 15.1. DDC1 Mode Timing Diagram
15.2. DDC2B + Slave & Master Mode Bus Interface
The built-in DDC2B+ I
2
C bus Interface features as follows
-
SLAVE mode (NT6862 is addressed by a master
which drives SCL signal)
-
MASTER mode (NT6862 addresses external device
and send out SCL clock)
-
Compatible with I
2
C bus standard
-
One default address (A0H) and one programable
address
-
Automatic wait state insertion
-
Interrupt generation for status control
-
Detection of START and STOP signals
The DDC2B+ will be activated as SLAVE mode initially.
Users can switch to MASTER mode by clearing the MODE
bit under either of these conditions listed as follows:
1. After entering to DDC1 function and clearing this bit, the
system will be changed from DDC1 to DDC2B+
MASTER mode operation.
2. After entering to DDC2B+ slave mode function and
clearing this bit, the system will changed from slave
mode into master mode operation.
As clearing MODE bit, system will send out a 'START'
condition and wait for user to put the calling address into
CH0/1TXDAT control register. Notice that user must
predetermine the direction of master mode transmission
before putting calling address.
Below is the DDC2B+ function with channel 0, and the
manipulation of channel 1 is the same as channel 0.