參數資料
型號： NT6862U
廠商： Electronic Theatre Controls, Inc.
英文描述： 8-Bit Microcontroller for Monitor
中文描述： 8位微控制器的監(jiān)控
文件頁數： 17/57頁
文件大小： 580K
代理商： NT6862U
NT6862-5xxxx
17
10. Watch-Dog Timer (WDT)
The NT6862 implements a Watch-dog timer reset to avoid
system stop or malfunction. The clock of the WDT is from
on-chip RC oscillator which does not require any external
components. Thus, the WDT will run, even if the clock on
the OSCI/OSCO pins of the device have been stopped.
The WDT time interval is about 0.5 second. The WDT must
be cleared within every 0.5 second when the software is in
normal sequence, otherwise the WDT will overflow and
cause a reset. The WDT is cleared and enabled after the
system is reset, and can not be disabled by the software.
Users can clear the WDT by writing 55H to CLRWDT
register ($0020).
as;
LDA
STA
#$55
$0020
Addr.
Register
INIT
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
$0020
CLR WDT
-
0
1
0
1
0
1
0
1
W
11. Interrupt Controller
The system provides two kinds of interrupt sources: NMI &
IRQ. The NMI can not be masked and if enabling NMI
interrupt sources, users can execute the NMI interrupt
vector anytime when sources are activated. The IRQ
interrupts can be masked by executing a CLI instruction or
setting the interrupt mask flag directly in the
μ
C status
register. In process IRQ interrupt, if the interrupt mask flag
is not set, the
μ
C will begin an interrupt sequence. The
program counter and processor status register will be
stored in the stack. The
μ
C will then set the interrupt mask
flag HIGH so that no further interrupts may occur. At the
end of this cycle, the program counter will be loaded from
addresses $FFFE & $FFFF, then transferring program
control to the memory vector located at these addresses.
For NMI interrupt,
μ
C will transfer execution sequence to
the memory vector located at addresses $FFFA & $FFFB.
When manipulating various interrupt sources, NT6862
divides them into two groups for accessing them easily.
One is NMI group and the other is IRQ group.
-
The NMI group includes INTE0, INTMUTE.
-
The IRQ group includes subgroup of IRQ0, IRQ1,RQ2:
IRQ0: DDC1/2B+ Channel 0 interrupt sources; It
includes INTS0, INTA0, INTTX0, INTRX0,
INTNAK0 and INTSTOP0 interrupts.
IRQ1: DDC1/2B+ Channel 1 interrupt sources; It
includes INTS0, INTA1, INTTX1, INTRX1,
INTNAK1 and INTSTOP1.
IRQ2: It includes INTADC, INTV, INTE1 and INTMR
interrupt sources.
The interrupt sources are shown below.
Nonmaskable Interrupt Group:
Interrupt
Meaning
Action
INTE0 INT
External 0 INT
It will be activated by the rising edge or falling edge of external interrupt pulse.
The triggered edge can be selected by EDGE0 bit.
INTMUTE
Auto Mute
It will be activated when the mute condition occurres (Hsync frequency
change). Please refer the synprocessor section for more details.
Maskable Interrupt Group:
Interrupt
Meaning
Action
INTADC
A/D Converion
Done
User activates the ADC by clearing the
CSTART
bit. When AD conversion is
done, this bit will be set.
INTV INT
Vsync INT
It will be activated as the rising edge of every Vsync pulse.
INTE1 INT
External 1 INT
It will be activated by the rising edge or falling edge of external interrupt pulse.
The triggered edge can be selected by EDGE1 bit.
INTMR INT
Timer INT
It will be activated as the rising edge of every when the Base Timer counter
overflows and counting from $FF to $00.
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