參數(shù)資料
型號: NT6862
廠商: Electronic Theatre Controls, Inc.
英文描述: 8-Bit Microcontroller for Monitor
中文描述: 8位微控制器的監(jiān)控
文件頁數(shù): 23/57頁
文件大?。?/td> 580K
代理商: NT6862
NT6862-5xxxx
23
12.3. PORT2: P20 - P27
PORT2, an 8-bit bi-directional I/O port (Figure 12.5), may be programmed as an input or output pin by the software control.
When setting the PT2DIR control bit to '0', its correspondent pin will act as an output pin. On the other hand, clear PT2DIR
bit to '1', act as input pin. When programmed as an input, it has an internal pull-up resistor. When programmed as an output,
the data to be output is latched to the port data register and output to the pin with push-pull structure. This port acts as input
port after reset.
Addr.
Register
INIT
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
$0002
PT2DIR
FFH
P27OE
P26OE
P25OE
P24OE
P23OE
P22OE
P21OE
P20OE
W
$0003
PT2
FFH
P27
P26
P25
P24
P23
P22
P21
P20
RW
$0010
ENADC
FFH
CSTA
-
-
-
ENADC3
ENADC2
ENADC1
ENADC0
W
$0029
CH1CON
FFH
ENDDC
MD1/
2
SRW
START
STOP
RXACK
TXACK
-
RW
12.4. PORT3: P30 - P31
PORT3 is an 2 bit bi-directional open-drain I/O port (Figure 12.6). Each pin of PORT3 may be bit programmed as an input or
output port with open drain structure. When PORT3 works as output, the data to be output is latched to the port data register
and output to the pin. When PORT3 pins that have '1's written to them, users must connect PORT3 with external pulled-up
resistor and then PORT3 can be used as input (the input signal can be read). This port output HIGH after reset.
P30
P31 include Schmitt Trigger buffers for noise immunity and can be configured as the I
2
C pins SDA0 & SCL0
respectively. If set ENDDC to LOW in CH0DDC control register, P30
and will be an open drain structure (Figure 12.6). After the chip is reset, this ENDDC bit will be in HIGH state and PORT3
will act as I/O pins.
P31 will act as SDA0 & SCL0 I/O pins respectively
Addr.
Register
INIT
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
$0004
PT3
FFH
-
-
-
-
-
-
P31
P30
RW
$0029
CH1CON
FFH
ENDDC
MD1/
2
SRW
START
STOP
RXACK
TXACK
-
RW
I/O
Data Out
Data In
Figure 12.6. PORT3
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